近年來，隨著人工智迅速發展，提升每單位面積之運算效能已成為關鍵，然而隨摩爾定律逐步逼近物理極限，僅以通道尺寸微縮已難獲顯著性能提升。為突破製程瓶頸，可從兩大方向著手：效能提升與面積微縮。
在效能提升方面，可透過低溫操作有效降低次臨界斜率、提升載子遷移率，以實現更高操作頻率及更低功耗，也可採用高遷移率材料，如鍺或 III–V 族化合物。面積微縮方面則可改變電晶體結構（如垂直式電晶體）或三維堆疊技術（如互補式場效電晶體 CFET）。
本論文綜合以上策略，選擇具垂直結構之鍺/矽 L 型場效電晶體（Ge/Si LFET）為研究對象，使用TCAD模擬其低溫下之電性表現，並與相同材料與幾何尺寸下與 CFET 進行比較。模擬結果顯示，LFET 中之垂直 Ge pMOS 可利用 (110) 晶面高載子遷移率優勢以及結構優勢，達成優於 CFET 的驅動電流與寄生電容抑制。
接著，本研究進一步探討 LFET 結構最佳化，包括側壁（spacer）與閘極氧化層介電常數、奈米片（sheet）數量與厚度等參數，最終提出分別適用於室溫與低溫操作的最佳結構設計，為低溫CMOS 元件之高效能應用提供具體指引。

In recent years, driven by the rapid advancement of artificial intelligence, the demand for high-performance semiconductor devices has surged. Enhancing computational efficiency per unit area has therefore become paramount. However, as Moore’s Law approaches its physical limits, mere channel-length scaling no longer yields significant performance gains. To overcome these fabrication bottlenecks, two principal strategies must be pursued: performance enhancement and footprint reduction.
Performance enhancement can be achieved through low-temperature operation, effectively reducing subthreshold swing and boosting carrier mobility to enable higher operating frequencies and lower power consumption, as well as by employing high-mobility materials such as germanium or III–V compounds. Footprint reduction, on the other hand, may be realized via novel transistor architectures (e.g., vertical transistors) or three-dimensional stacking technologies such as complementary FET (CFET).
This thesis adopts both approaches by focusing on the vertically oriented Germanium / Silicon L-shaped field-effect transistor (Ge/Si LFET). Using TCAD simulations, the low-temperature electrical characteristics of the Ge/Si LFET are evaluated and compared to those of a CFET with identical material composition and geometric dimensions. The results demonstrate that the vertical Ge pMOS channel, leveraging the high carrier mobility of the (110) crystal plane and its intrinsic structural advantages, delivers superior drive current and reduced parasitic capacitance relative to the CFET.
Subsequently, the study further explores structural optimization of the LFET, examining parameters such as spacer and gate-oxide dielectric constants, as well as the number and thickness of nanoscopic sheets. Based on these investigations, optimal device architectures for both room-temperature and cryogenic operation are proposed, offering concrete design guidelines for high-performance, cryogenic CMOS applications.

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