非晶氧化銦鎵鋅薄膜電晶體，因具優異薄膜均勻度、高載子遷移率與低溫製程，擁有可應用於液晶面板或可撓式基板上做為驅動與畫素開關元件之潛力，目前已引起熱烈的研究。然而，傳統氧化銦鎵鋅薄膜電晶體因源極欲通道間缺少如p-n接面足夠大的能障，故於零閘極電壓時漏電流較大，此一缺點使其在應用上仍存限制。為了克服此缺點，本研究利用不同蕭基接面及數種增強蕭基位障高度之結構降低其漏電流以改善薄膜電晶體特性。
第一部份為蕭基二極體的製備，由於氧化銦鎵鋅表面缺陷密度過高，與上接觸金屬無法形成良好的蕭基接面，藉由通入氧氣含量為20%之氧化銦鎵鋅，以及一8 nm之氧化矽鉿介面層，可以達到較佳的二極體之整流特性。於Au/HfSiO/O2-rich IGZO/Ti為結構的蕭基二極體，可獲得電流整流比為102，蕭基能障為0.73 eV。於Ag/HfSiO/Ti為結構的蕭基二極體，可得電流整流比為104，蕭基能障為0.83 eV。由實驗結果發現，此雙層介面層分別扮演不同的角色，O2-rich IGZO介面層可有效降低IGZO之表面缺陷密度，且能增加蕭基接面之空乏區寬度，減少電子穿透；HfSiO介面層可修補IGZO之表面態位密度，且能抑制上接觸金屬與氧化銦鎵鋅的相互擴散。
第二部分為氧化銦鎵鋅蕭基能障薄膜電晶體(IGZO SBTFTs)之製作。利用金、銀做為源極金屬，於源極與IGZO通道層之介面，依序沉積O2-rich IGZO與HfSiO介面層，由此雙層介面層結構，獲得合適之蕭基金半接面，成功製備IGZO SBTFTs，由實驗結果以金為源極金屬之蕭基薄膜電晶體，可獲得元件特性關閉電壓為0.02 V，電流開關比為2.90×106、次臨界擺幅為0.097 V/dec及載子遷移率為8.19 cm2/Vs。達成本論文之降低關閉電流、提升開關比、改善次臨限擺幅之目標。
本論文成功於低溫環境下製備蕭基能障層，且應用及改善氧化銦鎵鋅薄膜電晶體之漏電流問題，故此蕭基能障層可廣泛應用於各類基板，如矽基板、玻璃基板與軟性塑膠基板，於顯示器相關技術，應用深具潛力。

Amorphous indium gallium zinc oxide (α-IGZO) Schottky barrier thin-film transistors (SBTFTs) with O2-rich IGZO interlayer (IL) and HfSiO/O2-rich IGZO bilayer stack are fabricated and characterized. Significant improvement in device characteristics obtained from Schottky contact source is demonstrated and discussed. With stacking a 25-nm-thick O2-rich IGZO and 8-nm-thick HfSiO bilayer in the source region, experimental results show that the turn-off voltage of SBTFTs increases from -0.7 V to about 0 V, the turn-off current decreases from 10-10 A to 10-11 A, the on/off current ratio increases from 105 to 106, the subthreshold swing decreases from 0.204 V/dec to 0.097 V/dec, and the mobility increases from 7.15 cm2/Vs to 8.19 cm2/Vs.

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