NAND Flash 元件具有高整合性與高存取速度等優點，在今日手攜式3C產品廣泛應用的世代，其應用已成為行動產品的主力之一。本論文主要的目的為研究NAND Flash 產品中所使用到的周邊電路元件之可靠度與元件特性。由於NAND Flash 產品中的cell 元件在資料寫入或者抹除操作時需要高電壓18V 之電源供給，因此NAND Flash 產品的周邊電路元件:字元線驅動(Word line driver)電路便需要將上級電路的高電壓傳送至cell 元件，而在本論文中的研究針對於字元線驅動電路元件從OFF-state轉換至ON-state的過程中元件之可靠度研究，最後再討論不同長度的通道對元件可靠度的影響。
在第二級的字元線驅動電路中，所使用的高壓元件為增強型元件，元件的操作過程中不斷地從OFF-state轉換至ON-state，在這過程中，元件會經過高汲極電壓與高基板電壓之情況。從實驗結果顯示元件操作在高汲極電壓(VDS)的時候發生熱載子效應會在汲極端之飄移區產生嚴重的碰撞游離，這將會在Si/SiO2表面產生介面態(interface state) 造成IDlin 退化，並藉由TCAD模擬來驗證實驗結果。當元件操作在高基板電壓(VBS)時，會使元件內部之垂直電場提高，造成在通道下方以及飄移區下方之區域發生第二次的碰撞游離，將導致更多之載子生成並有機會在通道發生電子注入，造成在Gate Oxide裡面形成缺陷，這將會使閘極對通道的控制能力降低並造成元件的臨界電壓因此提高。
另一部分，主要探討不同長度之通道對元件之可靠度造成的影響。我們將不同通道長度之元件做stress實驗，從實驗結果顯示不同長度之元件退化的機制都相同，而且如同我們所預期短通道之元件的耐壓能力較差，IDlin與VTH之退化都較大。另外我們定義出元件之生命期(lifetime)，並歸納出不同通道長度對生命期的影響。

Recent years, NAND flash storage drive is one of the most important products used in mobile electric products. The NAND Flash device is with the advantages which are high integrated and fast storage speed. The main purpose of this thesis is about the reliability studies of NAND Flash Periphery devices. Since the NAND flash needs high voltage around 18V during program / erase operation, The Devices in NAND Flash Memory Periphery Circuitry in this thesis is word-line driver circuits, the devices have to pass high voltage from superior circuit to cell devices. The first part research in this thesis focused on the reliability issue which took place in the transition of the devices from OFF-state to ON-state, and last part, we discussed the impact of reliability on different channel length devices.
The second stage is the word-line driver circuit which used enhanced-mode NMOSFET. The devices operated in the transition from OFF-state to ON-state incessantly. In this switching process, the devices will be operated at high VDS and high VBS. From the experimental results, there is a critical impact ionization in the drain side drift region which caused by hot-carrier effect when device operated at high VDS, it will induced that interface state (Nit) are generate in the Si/SiO2 surface and cause IDlin degradation. The experimental results are verified by TCAD simulation. On the other hand, the vertical electric field inside device will increase when device operated at high VBS and induced secondary impact ionization below the region of channel and drift region, this mechanism will cause more carrier generation and may cause electrons injection into gate oxide, and resulting in the formation of defects inside the gate oxide, the gate control of the channel decreased and caused VTH increased.
The other part of this thesis, we research the different channel length of for the impact of the reliability of devices. We stressed the devices which are different channel length devices, as the experimental results, the degraded mechanism in different channel length devices are the same, and as we expected that the sustainable capability of the short-channel device is relatively poor, in short channel devices, IDlin degradation and VTH shift are relatively large. Besides, we defined the lifetime of devices and summarized the influence of different channel the length on the lifetime.

[1] L. Jae-Duk, H. Sung-Hoi, and C. Jung-Dal, "Effects of floating-gate interference on NAND flash memory cell operation," Electron Device Letters, IEEE, vol. 23, pp. 264-266, 2002.
[2] K. Taeho, D. Roberts, and T. Mudge, "Improving NAND Flash Based Disk Caches," in Computer Architecture, 2008. ISCA '08. 35th International Symposium on, 2008, pp. 327-338.
[3] K. Kim, "Technology for sub-50nm DRAM and NAND flash manufacturing," in Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, 2005, pp. 323-326.
[4] E. Takeda, N. Suzuki, and T. Hagiwara, "Device performance degradation to hot-carrier injection at energies below the Si-SiO<inf>2</inf>energy barrier," in Electron Devices Meeting, 1983 International, 1983, pp. 396-399.
[5] A. G. Sabnis. VLSI reliability,” in VLSI Electronic Microstructure Science, vol. 22, Academic Press, New York, Chapter 6, 1990.
[6] C. Hu, "“Advanced MOS Device Physics,” in VLSI Electronic Microstructure Science, 18, Academic Press, New York, Chapter3 " 1989.
[7] D. A. Neamen, "Semiconductor Physics And Devices, Basic Principles,thrid edition,Chapter 11.3," 2003.
[8] A. M. H. Noorashiqin, "A TCAD Analysis of the Impact of Starting Material Doping on 1.8V CMOS Threshold and Body Effect," The 5th Student Conference on Research and Development –SCOReD 2007 11-12 December 2007, Malaysia.
[9] J. D. Bude, "Gate current by impact ionization feedback in sub-micron MOSFET technologies," in VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on, 1995, pp. 101-102.
[10] M. M. J.D. Bude , M.R. Pinto I , R.W. Gregor , P.J. Kelley and C. W. L. R.A. Kohler , Y. Ma , R.J. McPartland , P.K. Roy , R. Singh "Secondary Electron Flash - a High Performance, Low Power Flash Technology for 0.35 pm and Below," IEDM, pp. 279-282.
[11] E. Takeda, Y. Nakagome, H. Kume, and S. Asai, "New hot-carrier injection and device degradation in submicron MOSFETs," Solid-State and Electron Devices, IEE Proceedings I, vol. 130, pp. 144-150, 1983.
[12] J. W. a. G. Taguchi, "The Mahalanobis-Taguchi strategy: a pattern technology system," 2002.
[13] S. Pin and J. J. Y. Kuo, "On the Enhanced Impact Ionization in Uniaxial Strained p-MOSFETs," Electron Device Letters, IEEE, vol. 28, pp. 649-651, 2007.
[14] K. M. Wu, J. F. Chen, Y. K. Su, J. R. Lee, Y. C. Lin, S. L. Hsu, et al., "Anomalous reduction of hot-carrier-induced ON-resistance degradation in n-type DEMOS transistors," Ieee Transactions on Device and Materials Reliability, vol. 6, pp. 371-376, Sep 2006.
[15] C. H. Tahui Wang, P. C. Chou, Steve S.-S. Chung, Member, IEEE, and Tse-En Chang, "Effects of Hot Carrier Induced Interface State Generation in Submicron LDD MOSFET’s," IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, YO. 9, SEPTEMBER 1994.
[16] J. G. Shih-hui CHEN, Meng-chyi WU, Tsung-yi HUANG, "Time-Dependent Drain- and Source-Series Resistance of High-Voltage Lateral Diffused Metal–Oxide–Semiconductor Field-Effect Transistors during Hot-Carrier Stress," 2003.
[17] J. F. Chen, T. Kuen-Shiuan, C. Shiang-Yu, W. Kuo-Ming, and C. M. Liu, "On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region," Electron Device Letters, IEEE, vol. 29, pp. 1071-1073, 2008.
[18] S. M. Ronald van Langevelde, IEEE, and Fran¸cois M. Klaassen, "Effect of Gate-Field Dependent Mobility Degradation on Distortion Analysis in MOSFET's," 1997.
[19] I. Dragica Vasileska and David K. Ferry Fellow, "Scaled Silicon MOSFET’s: Universal Mobility Behavior," 1997.
[20] M. N. Darwish, "An Improved Electron and Hole Mobility Model for General Purpose Device Simulation," 1997.
[21] V.-H. C. a. J. E. Chung, "Two-Stage Hot-Carrier Degradation and Its Impact on Submicrometer LDD NMOSFET Lifetime Prediction," IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 5,, MAY, 1995.