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研究生： 孫名儒
Sun, Ming-Ju
論文名稱： 高壓金氧半元件在相異操作情況下熱載子可靠度模型之研究
Investigation of Lifetime Model of High Voltage MOSFET Under Different Operation Mode
指導教授： 陳志方
Chen, Jone-Fang
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年： 2019
畢業學年度： 107
語文別： 英文
論文頁數： 79
中文關鍵詞： 高壓金氧半電晶體 、熱載子退化 、電腦輔助設計模擬 、生命週期
外文關鍵詞： HVMOSFET, hot-carrier-induced degradation, TCAD simulation, Lifetime
相關次數： 點閱：85  下載：1 
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    • 本論文主要在探討，N型通道高壓橫向擴散金屬氧化物半導體在不同操作區域下，其熱載子退化與機制之改變。
    首先，在前人的研究當中指出，在長時間的退化特性可以由短時間的加速測試而得到，而在此加速測試下得到的退化趨勢，可以藉由平移之方法重疊各曲線到通用退化曲線，而平移之倍率我們稱為比例係數(Scaling Factor)。而先前研究中亦提到比例係數對於元件壽命有著密切的關係，且此關係已經在一般N型金屬氧化物半導體中得到證實。然而，在本論文中我們將此觀念應用至高壓金屬氧化物半導體並從中獲得其生命週期關係式。 我們亦利用此關係建立生命週期模型，並且驗證之。
    再者，我們將會展示實驗設置與元件基本電性包含線性區與飽和區特性。我們亦會研究元件於次臨界區的退化特性。此外，我們也會探討元件可靠度與退化機制，例如:載子注入、碰撞游離與內部電場等等。並且我們的實驗將會藉由TCAD來模擬分析。

    最後，根據我們先前分析的元件退化機制，我們將提出一個基於元件各端點特性電流的模型。然而，我們的模型並不是用於所有操作條件下，因此我們會藉由TCAD模擬其退化，並觀察其內部變化如何影響元件退化機制。

    In the thesis, the N-type high voltage lateral diffused metal-oxide –semiconductor (N-HVLDMOS) hot-carrier-induced degradation and mechanism under different operation mode had been investigated.
    First, the previous work had shown that the long term degradation can be obtained from the short time stress, the degradation trend can be fit to one general degradation curve, the fitting factor is called scaling factor(S). The previous work had shown that scaling factor had some relationship with device life time, and it had been proved under usual N-type metal-oxide –semiconductor. However, in this thesis, the concept of scaling factor was applied to N-HVLDMOS to derive the lifetime equation. We would model the device lifetime, and then verified it.
    Sequentially, we would also present our experiment setup and the basic characteristic results including ID-VG linear region, ID-VG saturation region ID-VD and ISub-VG. We would also investigate the degradation of the device in the subthreshold. Also, the reliability issues and the degradation mechanism, such as hot carrier injection, impact ionization and electric field would also be introduced. Moreover, TCAD simulation would also be introduced to analyze the mechanism.
    Finally, according to the degradation mechanism we analyzed, we would present a model based on IS, VG and VD. However, our model was not ava available for all operation region, so we would use TCAD to simulation degradation mechanism and explain how it changed to influence the reliability.

    中文摘要 I Abstract III Acknowledgement V Content VI Table Captions IX Figure Captions X Chapter 1 1 1-1 Motivation of the thesis 1 1-2 Introduction of HV-LDMOS devices applications 2 1-3 Introduction of hot carrier reliability 4 1-4 Introduction of scaling factor 5 1-5 Introduction of hot carrier reliability 6 1-6 Introduction of technology computer aid design 7 1-7 About the thesis 8 Chapter 2 16 2-1 Introduction 16 2-2 Device structure description 16 2-3 Experiment methodology 17 2-3-1 Measurement setup 17 2-3-2 ID-VD measurement 17 2-3-3 ID-VG measurement 18 2-3-4 Isub-VG measurement 19 2-3-5 Simulation setup 20 2-4 Summary 21 Chapter 3 30 3-1 Introduction 30 3-2 Experiment setup and stress condition 30 3-3 Hot carrier degradation in on-state degradation 31 3-4 Scaling factor and power law in on-state degradation 33 3-5 Discussion of degradation at low gate voltage 34 3-6 Analysis of HV-LDMOS at low gate voltage 35 3-7 Discussion of degradation at high gate voltage 37 3-8 Analysis of HV-LDMOS at high gate voltage 38 3-9 Summary 40 Chapter 4 57 4-1 Introduction 57 4-2 Definition of available region in scaling factor model 58 4-3 Lifetime model in on-state 59 4-4 Subthreshold degradation and lifetime 60 4-5 Degradation mechanism in subthreshold 61 4-6 Summary 62 Chapter 5 71 5-1. Conclusion 71 5-2. Future work 73 References 74 Table2.1 The condition of parameter extraction 28 Table2.2 The parameter extracted results 29 Table 3.1 Stress condition of all devices 55 Table 3.2 Degradation of all devices 55 Table 3.3 Scaling factor of all devices 56 Table 3.4 Power law of VDG versus 1/s 56 Table 4.1 Power of channel current 69 Table 4.2 Stress condition in threshold 69 Table 4.3 Degradation of all devices 70 Fig 1-1 Automobile and IoT application [6] 10 Fig. 1-2a Cross section of NLDMOS transistor showing NDrift, Channel, Accumulation and Bird’s beak regions. [7] 10 Fig. 1-2b Schematic overview of an LDD n-MOSFET. [8] 11 Fig. 1-2c Schematic overview of an LDD n-MOSFET with STI structure. 12 Fig. 1- 3 hot carrier injection induced by impact ionization [10] 12 Fig 1-4 The degradation curve and universal curve [17] 13 Fig 1-5 The correlation between VD and 1/S [18] 14 Fig. 1-6 TCAD simulation tools and relationship. [19] 15 Fig.2-1 The n-type HV-MOSFETs with the LDD region 22 Fig.2-2 The net doping of HV-MOSFETs 22 Fig. 2 3 Agilent B1500A semiconductor device parameter analyzer. 23 (A) 3D complete view (B) Front Side (C) Back Side [25] 23 Fig. 2- 4 Shielding box 24 Fig. 2-5 ID-VG curve 25 Fig. 2-6 Linear current 25 Fig. 2-7 Saturation current 26 Fig. 2-8 Substrate current versus gate voltage 26 Fig. 2-9 Simulation results and measurement data 27 Fig. 3-1 experiment flow 41 Fig. 3-2 Degradation of (A) linear region (B) saturation region 42 Fig. 3-3 Damage region 43 Fig. 3-4 Degradation of all devices 44 Fig. 3-5 General degradation curve 44 Fig. 3-6 Irregular points and power law 45 Fig. 3-8 Y-direction field (A) Device D (B) Device A (C) Device E 48 Fig. 3-9 cutline of Y-direction 48 Fig. 3-10 power law interface 49 Fig. 3-11 Electric field (A) low gate voltage (B) high gate voltage 50 Fig. 3-12 Electric field (A) Device A (B) Device F 51 Fig. 3-13 Cutline of electric field 52 Fig. 3-14 II rate of the device (A) Device A (B) Device F 53 Fig. 3-15 II rate along the cutline 53 Fig. 3-17 The box location 54 Fig. 3-18 The simulation of two different damaged-region 54 Fig. 4-1 The correlation between VGD and 1/S 63 Fig. 4-2 The fitting result 63 Fig. 4-3 Linear degradation 64 Fig. 4-4 Universal curve 64 Fig. 4-5 Lon-term saturation 65 Fig. 4-6 1/S versus VDG. 65 Fig. 4-7 I-I rate of Device C and Device G 66 Fig. 4-8 I-I rate simulation (A) Device A (B) Device G 67 Fig. 4-9 Carrier density along the cutline 68 Fig. 4-10 Ratio about electrons and holes of all device 68

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