作者:黃耘緯 指導教授:張志文 共同指導教授:黃尊禧
本論文晶片皆採用TSMC CMOS 90-nm製程實現並以on wafer或on wafer circuit measurement with PCB bias network形式量測。
第一部份為整合設計W-band CMOS射頻接收機晶片，其子電路包含低雜訊放大器、混頻器及振盪器。低雜訊放大器的架構採用共源極與共閘極形成之疊接架構，並在第一級與第二級電路中加入自製電感達到最佳雜訊匹配；混頻器採用雙平衡架構，藉由移除RF訊號轉導級及將主電路開關部分電晶體偏壓於弱反轉區減低功耗；振盪器方面因94 GHz起振條件嚴苛，故本次設計採用基頻47 GHz壓控振盪器，再經由倍頻器升頻至94 GHz，除了降低起振難度也可藉由倍頻器隔離放大器寄生電容對共振腔之影響。
第二部份94 GHZ CMOS低LO功率環型次諧波混頻器主要目的在於減少VCO設計困難度。由於實驗室整合VCO難以在高頻下同時提供符合混頻器轉換增益的最佳LO功率，導致須大量耗費額外功耗故與第二章混頻器不同改以LO頻率的兩倍與RF訊號做混合。另外LO訊號以閘級、源級交錯饋入結合弱反轉區偏壓技術不僅能增加一倍頻LO訊號洩漏至RF端之隔離度更可以在維持原本閘極饋入時轉換增益及LO功率表現下改善匹配難度，節省匹配電路消耗之面積亦利於未來整合。
第三部份47 GHz CMOS電流再利用型壓控振盪器配合第三章次諧波混頻器LO頻率與轉換增益所需最佳功率來設計，電路採用電流再利用型架構，希望在與第三章次諧波混頻器整合下，在整個收發機系統中能提供更多功耗餘裕給負責放大增益的低雜訊放大器和功率放大器，且此次利用自發性轉導匹配(Spontaneous transconductance match, STM)技巧利用中心電感偵測輸出振幅差動態地平衡交互耦合電晶體對的轉導值，改善振幅差的現象。

Author: Yun-Wei Huang Advisor: Chih-Wen Chang Co-Advisor: Tzuen-Hsi Huang
This thesis presents the design of W-band front-end receiver, 94 GHz CMOS low LO power ring sub-harmonic mixer and 47 GHz current-reuse VCO, which are implemented in the TSMC 90-nm GUTM technology.
The first part of the thesis is an integration design of a W-band front-end receiver, which consists of a low amplifier (LNA), a voltage-controlled oscillator (VCO),and a ring mixer. The LNA having a five stage cascode to enhance the performance of power gain. An inductance has been added between the cascode transistors of the first and second stage of the LNA to optimize noise matching. The mixer uses the double-balanced structure. The power consumption is reduced by removing the RF signal input transistor and using the weak inversion biasing technique. In terms of the VCO, due to its harsh start-up conditions at 94 GHz, the fundamental frequency 47 GHz VCO is selected for this design. Further, using a frequency multiplier increases the fundamental frequency to 94 GHz. In addition to reducing the difficulty of start-up conditions, the frequency multiplier is used to isolate the influence of the parasitic capacitance of the amplifier.
The second part is the design of a 94 GHz CMOS low LO power ring sub-harmonic mixer. The purpose of this design is to reduce the difficulty of VCO design. Because of the VCO in the previous part is difficult to provide the optimal LO power to drive the mixer at 94 GHz, we choose twice the LO frequency to mix with the RF signal. In addition, the LO signal is injected into gate and source alternately, which can reduce the difficulty of matching and save the area consumed by the matching circuit.
The third part is the design of a 47 GHz current-reuse VCO, which is designed on the basis of the mixer requirement. The low power design can be achieved by current-reuse technique. In the whole transceiver system, it can provide more power consumption margin to the low noise amplifier and power amplifier. Using the spontaneous transconductance match (STM) technique, the central-taped inductor is used to detect the output amplitude difference to dynamically balance the transconductance value of the cross-coupled transistor pair, so as to improve the phenomenon of the amplitude difference.

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