從廣角攝影機所取得的影像，經常受到嚴重的桶狀扭曲(barrel distortion)影響。為了解決此一問題，我們通常會使用高次多項方程式，把已經扭曲的影像修正為未扭曲的影像。本論文乃針對桶狀扭曲的廣角攝影機影像修正進行討論。
為了修正扭曲影像，通常會取得待修正影像中，像素與扭曲中心的距離，以及像素與扭曲中心連線和水平線的夾角，以進行桶狀扭曲的修正。傳統的作法是用座標轉換器(CORDIC)的硬體來取得距離與夾角。這樣的修正流程需要大量的運算時間和更高的硬體成本。本論文提出一個低成本管線化的扭曲修正VLSI架構，並且對於數張從廣角攝影機擷取出來的影像進行桶狀扭曲修正，修正的結果優於傳統的方法。
所提出的VLSI架構使用Verilog硬體描述語言設計並在Altera EP20K600EBC652-1X FPGA作模擬，在相同的環境下與傳統方法相比較，我們的設計能有較低的硬體成本與較高的執行速度。硬體成本降至傳統方法的三分之一，工作時脈也提高為45.81MHz，並且把pipeline架構中不可避免的前置時間從91個clock cycle縮減成11個clock cycle。

Images captured with wide-angle cameras tend to have severe barrel distortions which pull points towards the optical center. To solve the problem, we can use a mathematical model based on polynomial equations to map the images from distorted image space to the corrected image space. This thesis focuses on the barrel distortion correction of wide-angle camera images.
To perform barrel distortion correction, usually we need to identify the distance of the pixel to be corrected and the distorted center of the wide-angle camera. Besides, we need to calculate the angle between the distance and horizontal axis. The traditional method obtains the distance and angle by using the coordinate rotation digital computer (CORDIC) based hardware design. This correction flow requires extensive computational time and higher hardware cost. A new lower-complexity technique for barrel distortion correction is presented in this thesis. The proposed distortion-correction model is applied to several images captured from wide-angle lens camera. Simulation results show that our method outperforms the traditional one.
Finally, a low-cost pipeline VLSI architecture for our method is presented. The VLSI architecture is designed with Verilog and implemented with Altera EP20K600EBC652-1X FPGA, respectively. Compared with the previous design, our chip achieves less hardware cost and higher clock rate.

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