近年來由於人工智慧發展迅速，許多領域都開始加入人工智慧進行應用。使用機器學習可以從大量的資料中進行學習並訓練模型，從而節省很多傳統運算方法所花費的時間。
此篇論文有三大主軸：加速半導體元件模擬速度、逆向元件設計、可解釋之人工智慧。此研究先以TCAD所生產之資料作為訓練資料，進行類神經網路之訓練，用以加速模擬之速度。TCAD為現今做元件模擬上常用的計算軟體，他可以進行複雜的三維元件的模擬，但是三維元件之模擬非常耗時，元件微縮之後又會考慮更多的物理原理。經過訓練的類神經網路可以做到短時間內精準地預測I-V曲線，達到與TCAD模擬一樣的效果。
傳統的模擬路徑式給予元件相關參數得出所需之I-V曲線，此方法必須要經過多次模擬才能找到合適的曲線。此研究我們希望逆轉這個過程，給予I-V曲線並得出我們所需要的元件參數。
以往對於人工智慧預測出來的結果，我們無法了解中間的過程，我們視其為一個黑盒子。現在我們希望藉由LRP這個分析方法來打開這個黑盒子，觀察我們訓練出來的類神經網路是否可以符合現今所熟知的物理原理。

In recent years, artificial intelligence has been growing rapidly. Many scientific fields have started to apply it. We can train the machine learning model to learn from large amount of data. This trained model can help us save a lot of time from traditional method.
There are three objectives in this research: speeding up the semiconductor simulation process, inverse device design and explainable AI. We will take the data produced by TCAD as the training data. The model trained by this data will be used to speed up the simulation process. TCAD is the most common software that used in the device simulation. It can do the 3D device simulation, but it is a time consuming process. As the device getting smaller, there will be more quantum physics need to be considered and cost more time in simulation. A trained ANN model can predict a result in a really short time and reach the same consequence as TCAD does.
In the traditional simulation path, we will input the device parameters and get the I-V curve. Now we want to reverse this process. We will input the I-V curve and get the device parameters.
Usually we seen neural network model as a black box because we don’t know how it works. In this research, we can use the LRP analyzation to open the black box, and observe the relation between AI and physics theory.

[1]Moore Gordon E. (1965-04-19). “Crammimg more devices onto integrated circuits”
[2] Haberfehlner, Georg. (2013). 3D nanoimaging of semiconductor devices and materials by electron tomography.
[3] Physics of Semiconductor Devices, S.M. Sze, Kwok K. Ng
[4] Korlapati, Keerti Kumar. (2014). Parametric Variation with Doping Concentration in a FinFET using 3D TCAD.
[5] D. Valencia, et al., Phys. Rev. Applied, 9, 044005, 2018.
[6] Nagashio, Kosuke. (2016). Graphene field-effect transistor application-electric band structure of graphene in transistor structure extracted from quantum capacitance. Journal of Materials Research. 32. 1-9. 10.1557/jmr.2016.366.
[7] Dubey, Sarvesh & Tiwari, Pramod & Jit, S.. (2010). A two-dimensional model for the potential distribution and threshold voltage of short-channel double-gate metal-oxide-semiconductor field-effect transistors with a vertical Gaussian-like doping profile. Journal of Applied Physics. 108. 034518-034518. 10.1063/1.3460796.
[8] Tawseef A. Bhat, M. Mustafa, M.R. Beigh (2015). Study of Short Channel Effects in n-FinFET Structure for Si, GaAs, GaSb and GaN Channel Materials. Journal of Nano- and Electronic Physics Vol. 7 No 3, 03010(5pp) (2015)
[9] V. K. Mishra and R. K. Chauhan, "Comparison of multiple fin heights for increasing drain current in N-FinFET," 2013 International conference on Circuits, Controls and Communications (CCUBE), Bengaluru, 2013, pp. 1-5, doi: 10.1109/CCUBE.2013.6718579.
[10] K. Lee, R. He, H. Huang, C. Yeh, I. Li and O. Cheng, "A study of fin width effect on the performance of FinFET," 2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, Hsinchu, 2015, pp. 503-504, doi: 10.1109/IPFA.2015.7224443.
[11] T. V. Singh and M. Jagadesh Kumar, "Effect of the Ge mole fraction on the formation of a conduction path in cylindrical strained-silicon-on-SiGe MOSFETs", Superlattices Microstruct., vol. 44, pp. 79-85, 2008.
[12] W. Zhang and J. G. Fossum, "On the Threshold Voltage of Strained-Si - Si 1 x Ge x MOSFETs", IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 263-268, 2005.
[13] I. S. Up, S. Si, T. Previous, S. Si, T. Subsections, S. Si, et al., 2.1 Substrate Strain, pp. 2-4, 2016.
[14] N. A. F. Othman, S. F. W. M. Hatta and N. Soin, "Performance of 7nm stress-engineered nFinFETs based on stressors consideration for different channel material," 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, 2016, pp. 267-271, doi: 10.1109/IPFA.2016.7564297.
[15] Othman, N.A.F., Hatta, .F.W.M. & Soin, N. Impact of Channel, Stress-Relaxed Buffer, and S/D Si1−xGe x Stressor on the Performance of 7-nm FinFET CMOS Design with the Implementation of Stress Engineering. Journal of Elec Materi 47, 2337–2347 (2018). https://doi.org/10.1007/s11664-017-6058-8
[16] arXiv:2003.05991 [cs.LG]
[17] “Deep Taylor Decomposition of Neural Networks”, Gregoire Montavon, Sebastian Bach, Alexander Binder, Wojciech Samek, Klaus-Robert Muller
[18] Montavon, G., Lapuschkin, S., Binder, A., Samek, W., M¨uller, K.R.: Explaining
nonlinear classification decisions with deep Taylor decomposition. Pattern Recogn.
65, 211–222 (2017)