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研究生: 唐嘉鴻
Tang, Jia-hong
論文名稱: 晶片網路之蟲洞繞送機制電路設計
Design of a Wormhole Switch Circuit for Network on a Chip
指導教授: 卿文龍
Chin, Wen-Lung
學位類別: 碩士
Master
系所名稱: 工學院 - 工程科學系
Department of Engineering Science
論文出版年: 2013
畢業學年度: 101
語文別: 中文
論文頁數: 56
中文關鍵詞: 晶片網路蟲洞交換系統晶片虛擬通道
外文關鍵詞: Network-on-chip, NoC wormhole switching virtual channel
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  • 隨著半導體技術的蓬勃發展,單一晶片上整合越來越多不同功能的模組,這樣的晶片我們稱之為系統單晶片(system on chip, SoC)。前瞻微處理器匯流排架構(Advanced Micro-controller Bus Architecture,簡稱AMBA)是一個被廣泛運用於系統單晶片上的匯流排架構,其提供了一套標準的匯流排協定,用以連結晶片上的各個元件。但隨著在系統單晶片上整合越來越多不同功能的模組,使得傳統的匯流排已經無法快速處理大量的內部通訊,進而造成整體系統的效能降低。因此,近年來開始有許多研究主題是探討晶片內部通訊的問題,其中最熱門的非晶片網路(Network on Chip, NoC)莫屬。
    在本篇論文中,我們對晶片網路的相關議題做探討,從晶片網路中的交換器、網路介面(Network Interface),到網路拓樸(Network Topology)、交換技術,路由演算法,都會一一作介紹,並說明其硬體電路架構的實現。而本篇論文實現一個晶片網路,其交換技術採用蟲洞交換(wormhole switching),網路拓樸採用網狀拓樸,交換器數量為9個,並且增加了虛擬通道(Virtual Channel)的方法,封包(Packet)在交換器中採用蟲洞交換與虛擬通道方式進行傳送,進而達到快速資料傳送並降低資料傳輸延遲(latency)的目的。我們所實作的電路在TSMC 90奈米製程下,可以達到166.6 MHz的運作速度。

    With the advances in silicon technology, more and more complicated hardware components can be integrated into a single chip. Hence, the System-on-Chip (SoC) design method becomes popular in recent years. Advanced Micro-controller Bus Architecture (AMBA) is an on chip bus architecture widely used in SoC. It provides a standard bus protocol to connect every component on the chip. As SoC integrates more hardware components, traditional bus architecture cannot process heavy internal communication quickly which leads to degradation of whole system performance. Recently, there are many papers research some issues about internal communication on chip and the most popular trend is the Network on Chip (NoC).
    In this thesis, we discuss issues about NoC. We will introduce network interface, network topology, switching techniques and routing algorithm on NoC, together with the hardware architecture. We will implement a popular NoC scheme: wormhole switching. The technique of wormhole switching uses the virtual channel for packet transmission. By adopting the mesh topology as the network topology, to accommodate 9 intellectual properties (IPs), 9 wormhole switches are required. Our design can achieve fast data transfer and low latency. According to physical implementation data, our design can operate at 166.6 MHz properly using the TSMC 90 nm technology.

    中文摘要 i 英文摘要 ii 誌謝 iii 目錄 iv 表目錄 vii 圖目錄 viii 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機 5 1.3 論文架構 7 第二章 晶片網路 8 2.1 網路拓樸 8 2.1.1 Single-Hop(單跳) 8 2.2.2 Multi-Hop(多跳) 9 2.2 路由演算法 14 2.3 交換技術 15 2.4 交換器 20 2.4.1 路由器(Router) 20 2.4.2 緩衝器(Buffer) 20 2.4.3 仲裁器(Arbiter) 21 2.5 網路介面 22 第三章 所提出的晶片網路設計 23 3.1 封包格式 23 3.2 網路拓樸及路由演算法的選擇 25 3.2.1網路拓樸 25 3.2.2 路由演算法 26 3.3 資料交換機制與緩衝器規劃 27 3.3.1 Virtual Channel數量 27 3.4 額外緩衝區設計 29 第四章 交換器硬體架構及實作 33 4.1設計方法(Design Methodology) 33 4.2 硬體運作流程 35 4.2.1 Routing(路由區) 36 4.2.2 Flit Switch(Flit交換區) 37 4.2.3 Output(輸出區) 38 第五章 模擬與驗證 39 5.1 模擬環境 39 5.1.1 模擬環境的建立 39 5.1.2 模擬結果與分析 45 5.2 硬體電路實現 50 第六章 結論與未來展望 51 參考文獻 54

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