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研究生: 顏士敦
Yen, Shih-Tun
論文名稱: 利用快速可編程邏輯閘陣列之互連網路以提高訊息傳遞之效能
Exploiting High Speed FPGA Interconnect to Improve Performance of Message Passing
指導教授: 張大緯
Chang, Da-Wei
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2011
畢業學年度: 99
語文別: 英文
論文頁數: 36
中文關鍵詞: Multi-ARM訊息傳遞訊息傳遞介面MPICH2可編程邏輯閘陣列互聯網路
外文關鍵詞: Multi-ARM, message passing, MPI, MPICH2, FPGA interconnect
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  • 我們有一個利用快速FPGA互聯網路連結六個使用ARM核心的嵌入式Linux系統的Multi-ARM模組化平台。然而目前此FPGA互聯網路無法被MPICH2所用。在這份論文中我們將MPICH2函式庫移植到Multi-ARM平台上,撰寫FPGA在此平台上的驅動程式並修改原本MPICH2函式庫中的乙太網路模組使其支援此FPGA互聯網路。我們將連線範圍只在此一平台之內的網路連線從原本的乙太網路介面重新導向到我們寫的FPGA驅動程式,使這些連線改利用FPGA交換網路來進行溝通。這份論文的主要貢獻是讓使用訊息溝通介面的程式可以在Multi-ARM平台上執行並利用其快速的FPGA交換網路以增進效能。另外我們擴充FPGA驅動程式使其可以蒐集所有連線的詳細傳輸數據,可作為離線情況下剖析應用程式之用。最後我們用NPmpi測試程式進行FPGA互聯網路的傳輸頻寬量測,量得最高傳輸速度達到181Mbps,將近是原本乙太網路三倍快的速度。

    In this thesis, based on a Multi-ARM modular platform which consists of six ARM-based embedded Linux systems and a fast FPGA interconnect, we port the MPICH2 library to the Multi-ARM platform to we allow MPICH2 to exploit the fast communication of the FPGA. To exploit the FPGA interconnect, we write a FPGA driver and modify the existing Ethernet module of MPICH2 to redirect intra-platform communications to this driver, as through the FPGA interconnect. Our main contribution is to enable MPI applications to run on the Multi-ARM platform, exploiting its fast FPGA interconnect to improve execution performance. In addition, we extend the FPGA driver to collect per-connection statistics with almost no overhead. According to the NPmpi benchmark, the maximum throughput of FPGA is 181Mbps, almost 3 times faster than existing fast Ethernet interface.

    Contents CONTENTS VII LIST OF FIGURES VIII LIST OF TABLES X CHAPTER 1. INTRODUCTION 1 CHAPTER 2. RELATED WORK AND BACKGROUND INFORMATION 3 2-1. Related Work 3 2-2. Introduction to MPICH2 3 CHAPTER 3. DESIGN AND IMPLEMENTATION 9 3-1. Multi-ARM Platform Overview 9 3-2. Modifying MPICH2 to Redirect Network Traffic to FPGA Interconnect 12 3-3. Design of FPGA Interconnect Driver 17 3-4. Simulating FPGA Interconnect with Kernel Socket 23 CHAPTER 4. EVALUATION 25 4-1. Introduction to Benchmark Suites 25 4-2. Execution Environment 26 4-3. Experimental Results 27 CHAPTER 5. CONCLUSION AND FUTURE WORK 33 REFERENCE 34

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