本研究利用磁控濺鍍方式製備以氮氧化鉭作為電荷捕捉層之金屬-氧化物-氮化物-氧化物-半導體(MONOS)結構電容器，以相同製程方式分別製作Al/SiO2/Si (MOS)、Al/Al2O3/SiO2/Si (MOOS)、Al/TaOxNy/SiO2/Si (MNOS)、Al/Al2O3/TaOxNy/SiO2/Si (MONOS)等疊層結構並改變特定層厚度，分別進行基礎材料分析，分析疊層之外觀與厚度、結晶狀態、元素分布與成分組成，並以電性分析研究造成遲滯窗口出現的捕捉能態位置與行為。材料分析方面，本研究以高解析穿透式電子顯微鏡(HRTEM)分析元件之疊層外觀與厚度，確認準確之疊層厚度以及有無過渡層存在，並判斷結晶性；以能量散佈分析儀(EDS)分析疊層之元素分布趨勢，了解成分組成；以X光光電子能譜儀(XPS)分析獲得TaOxNy單層之詳細成分組成，以及疊層之成分與鍵結型態；以低掠角X光薄膜繞射儀(GIAXRD)分析TaOxNy單層之結晶性。電性分析方面，本研究以半導體參數分析儀(Agilent 4156C)執行定電流應力量測(Constant current stress (CCS) measurement)，以及元件漏電流量測；以阻抗分析儀(Agilent 4294A)量測元件在各頻率下之電容-電壓曲線(Capacitance-Voltage Curve)以獲得C-V遲滯窗口，並將各參數之影響分別討論。根據各疊層結構以及以HRTEM分析各層之厚度，吾人定義出各元件之代號(如：MOS(4.5)、MONOS(9.4/4.4/4.5))。並由XPS分析發現在氮化層內具有不同比例之Ta-N鍵結以及Ta-O之鍵結，經由換算得知元素比例為Ta : O : N = 1 : 0.557 : 0.468，故吾人遂將此層命名為氮氧化鉭(TaOxNy)，並由GIAXRD確認為非晶性。由各疊層元件在變頻率(1k ~ 5M Hz)下之C-V遲滯曲線來看，MOS系列因無C-V遲滯窗口，故無窗口與頻率之相關性；MOOS系列元件僅有微量C-V遲滯窗口，窗口大小不隨頻率增加而改變；MONOS系列元件，除部分頻率外，各元件本身之C-V遲滯窗口大小皆不隨頻率增加改變。MNOS系列元件，則因C-V曲線不穩且幾無C-V遲滯窗口存在，而難以辨認其相關性。MOS系列元件因無C-V遲滯窗口，故SiO2厚度(2.7 ~ 9.0 nm)上升與窗口大小無相關性，但元件於載子累積(carrier accumulation)時因漏電產生之曲線下落現象隨著SiO2厚度上升而不再發生；MOOS系列元件之C-V遲滯窗口隨著SiO2厚度上升而對總厚度呈線性上升，表示其等效捕捉電量(ΔQeff, C/cm2 )為定值。而隨Al2O3厚度(9.4 ~ 13.7 nm)上升，C-V遲滯窗口對總厚度亦呈線性上升，故等效捕捉電量亦為定值。對於MOOS系列元件來說，改變厚度未對等效捕捉電量有明顯影響；MONOS系列元件之C-V遲滯窗口隨著SiO2厚度上升而對總厚度呈線性下降，等效捕捉電量隨之下降，原因為SiO2厚度上升造成電荷穿隧進入TaOxNy機率下降。而隨TaOxNy捕捉層厚度上升，C-V遲滯窗口對總厚度呈現非線性上升，等效捕捉電量隨著TaOxNy厚度(4.4 ~ 12.6 nm)上升而急遽上升，代表電荷捕捉能態主要位於TaOxNy層。在CCS量測推算電荷捕捉位置中，MOS元件之電荷捕捉可視為平均分布於SiO2層內；MOOS元件之電荷捕捉可視為平均分布於Al2O3與SiO2疊層，但在小電流時有較多電荷捕捉位在Al2O3層內較遠離Al2O3/SiO2界面處、大電流時有較多電荷捕捉位在Al2O3層內較接近Al2O3/SiO2界面；MNOS元件中可將電荷捕捉視為平均分布於TaOxNy與SiO2整個疊層，但在小電流時有較多電荷捕捉位在TaOxNy/SiO2界面處、大電流時有較多電荷捕捉位在TaOxNy內接近TaOxNy/SiO2界面處；MONOS元件在小電流下，有較多電荷捕捉位在TaOxNy層內接近TaOxNy/SiO2界面處、大電流時有較多電荷捕捉位在TaOxNy層內接近Al2O3/TaOxNy界面處。MOOS系統內吾人以假設捕捉平均位於Al2O3層內以及假設捕捉位於Al2O3/SiO2界面之方式，計算各元件之電荷分布影響因子(

In this study, the metal-oxide-nitride-oxide-semiconductor (MONOS) capacitors with TaOxNy charge trapping layer are fabricated by magnetron sputtering, and several structures like MOS (with an Al/SiO2/Si structure), MOOS (with an Al/Al2O3/SiO2/Si structure), and MNOS (with an Al/TaOxNy/SiO2/Si structure) are also fabricated by the same process. In addition, the thicknesses of particular layers in the devices above are varied through different growth time durations. In order to realize the behavior and location of the trap states which determine the Capacitance-Voltage (C-V) hysteresis window width, the electrical measurements are carried out by Agilent 4156C semiconductor parameter analyzer and Agilent 4294A LCR meter. Also, the basic material characteristics of the devices are analyzed by high resolution transmission electron microscopy (HRTEM), energy-dispersive X-ray spectroscopy (EDS), grazing incident angle X-ray diffraction (GIAXRD), and X-ray photoelectron spectroscopy (XPS).The devices are named according to the device structure and thickness of each layer observed by HRTEM, for example, MOS(4.5) or MONOS(9.4/4.4/4.5), and also the interfaces of the dielectric layers are confirmed by HRTEM. Based on the results from XPS analysis, there are several compositions of Ta-N bonding and small amount of Ta-O bonding in the nitride layer, and the atomic ratio is estimated as Ta : O : N = 1 : 0.557 : 0.468; hence, it is named TaOxNy. Furthermore, TaOxNy is confirmed as amorphous phase by GIAXRD. Based on the C-V hysteresis curves of each device measured at different frequencies (1k ~ 5M Hz). No C-V hysteresis window is observed for MOS devices, and thus there is no correlation with frequency. MOOS devices show a narrow hysteresis window width, which stays constant at different frequencies. MONOS devices show a constant hysteresis window width at different frequencies. MNOS devices do not show dependence between hysteresis window and frequency since there is no hysteresis window and the C-V curves are not stable. As for MOS devices, the hysteresis window widths are all negligible for different SiO2 thicknesses (2.7 ~ 9.0 nm). However, with increasing SiO2 thickness, the drop of C-V curves at carrier accumulation region due to leakage current can be reduced; in MOOS devices, the hysteresis window width increases linearly to total thickness as increasing thickness of SiO2, and the effective trap charge (ΔQeff, C/cm2) is constant. Besides, the hysteresis window width increases linearly to total thickness as increasing thickness of Al2O3 (9.4 ~ 13.7 nm), too, and the effective trap charge is constant. There is no significant effect on effective trap charge by changing thickness of layers in MOOS devices. For MONOS devices, the hysteresis window width decreases linearly to total thickness as increasing thickness of SiO2, and the effective trap charge decreases as well. The tunneling probability declines as increase of SiO2 thickness, which results in less charge tunneling into TaOxNy trapping layer. The hysteresis window width increases non-linearly to total thickness as increasing thickness of TaOxNy (4.4 ~ 12.6 nm), and the effective trap charge increases sharply as well, which means the trap state determining the hysteresis window width mainly located on TaOxNy layer.
In CCS measurement, it is observed that the charges are trapped uniformly in SiO2 in MOS device. In MOOS device, the charges are substantially trapped over Al2O3 and SiO2, but more traps are located on Al2O3 layer away from Al2O3/SiO2 interface at low applied current, and more traps are located on Al2O3 layer near Al2O3/SiO2 interface at high applied current. In MNOS device, the charges are substantially trapped over TaOxNy and SiO2, but more traps are located on TaOxNy/SiO2 interface at low applied current, and more traps are located on TaOxNy layer near TaOxNy/SiO2 interface at high applied current. In MONOS device, traps are mainly located on TaOxNy layer near TaOxNy/SiO2 interface at low applied current, and mainly located on TaOxNy layer near Al2O3/TaOxNy interface at high applied current.
In MOOS devices, by assuming that traps are uniformly located on Al2O3, or located at Al2O3/SiO2 interface, γ value is calculated for each device under two assumptions. Through the calculated γ value, the dependence of effective trap charge to thickness of the dielectric layers, and trapping center estimated by CCS measurement, the trap states which determine the hysteresis window width are confirmed to be located on Al2O3 near the Al2O3/SiO2 interface in MOOS series devices. In MONOS devices, by assuming that traps are uniformly located on TaOxNy, or located at Al2O3/TaOxNy interface, or located at TaOxNy/SiO2 interface, γ value is calculated for each device under the three assumptions. Through the calculated γ value, the dependence of effective trap charge to thickness of the dielectric layers, and trapping center estimated by CCS measurement, the trap states which determine the hysteresis window width are confirmed to be mainly located on TaOxNy layer, but it would be near to the TaOxNy/SiO2 interface when the operated voltage/current is relatively low (like the C-V sweep range we set, ±3 V). That is, in MONOS series devices, the hysteresis window width measured in the C-V curve in this thesis is caused by the trap states in TaOxNy layer near to TaOxNy/SiO2 interface. By measuring C-V curves and CCS of the devices with different stacking structure and thickness, the trapping behavior and location of the trap states which determine the hysteresis window widths are systematically discussed.

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