本研究提出一套結合串流資料傳輸與部分重組之 FPGA 推論加速架構，透過有限數量之硬體加速器串聯與可重組區域的重複使用，達成節省資源並提升推論效率之目的。部分重組可於執行期間動態載入對應的硬體加速模組，使資源受限之FPGA具有得以支援規模較大的神經網路模型之適應性，然而需將中間特徵資料寫回外部記憶體。另一方面，串流式架構雖能使相鄰運算模組直接傳遞資料，但須同時配置模型所需之硬體模組，容易受到有限資源限制。因此本研究將串流資料傳輸與部分重組機制加以整合，在資源受限環境下兼顧資料傳輸效率與架構適應能力。
本系統具備三項主要設計。首先，將多個硬體加速器組成串流運算群組，使同一群組內前一硬體模組之輸出可直接傳遞至下一硬體模組；其次，透過部分重組機制動態替換不同推論階段所需之硬體模組，並搭配管線化執行機制設計，藉此降低載入模組所產生的等待時間；最後，建立一套推論時間估計模型，依據各階段之配置時間、執行時間與相依關係，估計不同批次大小、加速器串聯數量及群組配置下之推論時間與資料吞吐量，作為架構配置與效能評估之參考。
本研究以 AMD Kria KV260 作為驗證平台，並採用MobileNetV1 模型測試。實驗結果顯示，相較於未串聯硬體加速器之部分重組配置，本研究提出的架構可降低 19.4% 與28.1% 的總推論時間。此外，推論時間估計模型與實際量測結果呈現相近的效能變化趨勢，各配置之平均相對誤差介於 1.0% 至 8.4% 之間。本研究所提出之架構能在有限 FPGA 資源下改善推論效率，並保留依據模型運算階段動態調整硬體功能之能力，證明結合串流資料傳輸與部分重組技術應用於 FPGA 推論加速器之可行性。

This study presents an FPGA-based neural-network inference accelerator that integrates streaming data transfer with partial reconfiguration to address the conflicting requirements of low data-movement overhead and limited programmable-logic resources. Accelerator modules are organized into streaming groups so that intermediate features pass directly between adjacent layers, while reconfigurable partitions are reused across inference stages to support networks whose total resource requirements exceeds the available FPGA capacity. An asynchronous pipeline overlaps configuration and execution when resource and data dependencies permit. A recursive timing model estimates inference throughput for different batch sizes and hardware configurations, characterized by the number of accelerators per group and the number of groups. The architecture is evaluated on an AMD Kria KV260 using an INT8-quantized MobileNetV1. Relative to a partial-reconfiguration baseline without accelerator chaining, the proposed reduce total inference latency by 19.4% to 28.1%, respectively. Predicted throughput follows the measured trends, with mean relative errors of 1.0 to 8.4%.

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