本論文中，我們主要研究雙軸基板應變矽技術於n型金氧半場效電晶體直流特性與閃爍雜訊響應的分析，這裡包括了有使用浮層源/汲極結構以及利用化學機械式研磨矽鍺虛擬基板以提高其品質。我們也成功的製作了高介電/金屬閘極-鈦/二氧化鉿/(三氧化二鋁)[Ti/HfO2/(Al2O3)]於不同重組表面(reconstructed-surface)的n型砷化銦金氧半電容與n型三五族金半場效電晶體搭載四族材料的異質介面源/汲極。
　　首先，浮層源/汲極結構用於n型應變矽金氧半場效電晶體的效用我們將從不同閘極尺寸的電性分析來探討其優點。此結構的應變矽元件在大尺寸(W/L=10um/10um)的時候提升了額外的11%的電流驅動力，而於小尺寸元件(W/L=0.15um/0.15um)的時候提升了的24%的源極電流，從這裡我們可以發現明顯的尺寸負載效應於沒有使用浮層源/汲極結構的應變矽元件，這主要是由於在形成鈷矽化合物時會讓擴散於矽鍺虛擬基板的鍺原子聚集析出於源/汲極區域，這也是導致源/汲極串連阻值提高的原因。
　　接著，由於SiGe緩衝層與基材的堆積差排引起垂直晶格的釋放所形成了交叉排線的表面形狀會造成表面的不平整，進而影響應變矽通道與二氧化矽閘極氧化層間的平整度，因此我們利用化學機械式研磨的技術來改善SiGe緩衝層表面的的平整，來改善閘極氧化層與通道介面的品質。藉由此介面品質的提升，3.5%的電流增益與大約30倍閃爍雜訊的改善，更甚的是此優點在於大電壓的操作條件下會更加明顯，這也間接地使用了電性來證實了通道表面品質的改進。
　　我們也以鈦/二氧化鉿/(三氧化二鋁)於不同重組表面的n型砷化銦金氧半電容來探討了高介電材料與砷化銦介面的反應。(1×1)的砷化銦表面元件展現了低頻率相依的電容值離散特性，相較於全部相同電性離子的(2×4)的砷化銦表面，等量陽離子與陰離子的(1×1)的砷化銦表面的確有助於抑制氧化反應的進行，進而改善了電容特性。
　　最後，我們完成的第一個n型三五族通道搭載四族材料異質介面源/汲極的金半場效電晶體。利用超高真空化學氣相沉積系統我們成功地達成選擇性磊晶成長鍺材料於砷化鎵基板；為了增加電流驅動力，我們設計了額外10奈米的的n型砷化銦鎵於90奈米的n型砷化鎵通道上形成了雙通道的結構，在電流特性上，開/關比達到1000倍；而為了提升閘極金半蕭基能障，寬能隙晶格匹配的磷化銦鎵也用以當作金半介面的介電層，實驗結果在閘極漏電上，此結構能達到與一般的鈦/砷化鎵元件同等的漏電級數。

　　In this dissertation, the biaxial substrate-strained silicon technology including the employment of raised source/drain structure and improved SiGe virtual substrate quality by the treatment of chemical mechanical polishing process on the characteristics of n-type MOSFETs have been systematically studied by using DC measurement and flicker noise response. We have also successfully fabricated the metal-gate/high-dielectric Ti/HfO2/(Al2O3) on different reconstructed-surface n-type InAs MOSCAPs and the first demonstration of n-type III-V metal-semiconductor field-effect transistors featuring with IV group material hetero-junction source/drain.
　　Firstly, the electrical characteristics for n-channel strained-Si metal-oxide-semiconductor field-effect-transistors combining raised source/drain structure and cobalt silicide have been studied with various gate pattern sizes. The strained-Si device with raised source/drain structure provides an additional driving current enhancement (up to 12%) for large-area devices at W/L = 10 um/10um. Further improvement of 24% for device areas down to W/L = 0.15um/0.15um indicates that obvious pattern loading effects exist in strained-Si without raised S/D case, which mainly due to the formation of up-diffused germanium agglomerated at source/drain region, which is also responsible for the increased source/drain series resistance.
　　Secondarily, utilizing chemical mechanical polishing procedure to reduce SiO2/Si roughness induced from cross-hatching of SiGe virtual substrate in strained-Si nMOSFETs has been investigated. Due to the smoother SiO2/Si interface, an additional 3.5% driving current and 11% transconductance enhancements are found in strained-Si devices with a gate length = 0.5um on CMP-treated SiGe virtual substrate. Additional, strained-Si devices with CMP process exhibit the better flicker noise performance, 1.5 orders of lower flicker noise over 1-100 Hz was obtained for strained-Si devices with CMP introduction. And we observed that carrier number fluctuation, just not the unified model, is more suitable to interpret the mechanism of flicker noise in strained-Si devices with CMP process. Under larger gate overdrive voltage, where carriers are almost transported nearly to surface, the improvement becomes more obvious indicating that the CMP process provides a smoother SiO2/strained-Si channel interface for biaxial substrate-strained Si device.
　　Thirdly, we report the characteristics of high-dielectric HfO2/(Al2O3) on different reconstructed-surface n-type InAs MOSCAPs. The HfO2/Al2O3 gate dielectric films deposited on InAs were used to study the interfacial reaction. Compared with (2×4)-surface sample, improvements of capacitance-voltage characteristics for (1×1)-surface sample with lower frequency-dependent capacitance dispersion and higher inversion capacitance are attributed to lower indium composition and less arsenic oxide at Al2O3/InAs interface, as confirmed by x-ray photoelectron spectroscopy. It indicates that the equivalent dangling bond of cations and anions on (1×1)-surface sample tends to avoid the oxidization process and become less pinning.
　　Eventually, the demonstration of n-type III-V metal-semiconductor field-effect transistors with IV group material hetero-junction source/drain technology was reported for the first time. A selective epitaxial growth of germanium in the recessed GaAs source/drain regions is successfully developed by using ultra-high vacuum chemical vapor deposition system. The dual channel structure included an additional 10-nm higher mobility n-In0.2Ga0.8As layer on n-GaAs channel is introduced to further improve the device performance. The n-MESFET combined embedded-Ge S/D with In0.2Ga0.8As/GaAs channel exhibits the good transfer properties with drain current on/off ratio of ~103. Due to the small barrier height of Ti/In0.2Ga0.8As schottky contact, a lattice-matched wide bandgap In0.49Ga0.51P dielectric layer is also integrated into the device architecture in order to build a higher electron schottky barrier height for gate leakage current reduction. Ti/InGaP/n-In0.2Ga0.8As schottky diode shows a comparable leakage level to Ti/n-GaAs with 2×10-2 A/cm^2 at gate voltage of -2.0 V.

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