Part 1
本論文中，研究熱去離子水清洗所造成的晶圓表面粗糙及應力對元件的電性特性如導通電壓、飽和電流、漏電流及崩潰電壓的影響。此外並研究熱去離子水對薄氧化層之電性如崩潰電壓及崩潰電荷的影響。吾人使用原子力學顯微鏡(AFM)來偵測晶圓表面的粗糙度及使用電容-電壓(C-V) 量測來調查介面陷阱電荷密度，結果發現熱去離子水清洗會增加晶圓表面粗糙與應力並導致元件特性如導通電壓、飽和電流及漏電流等的不均勻分佈及降低薄氧化層的崩潰電壓及崩潰電荷。

Part 2
吾人研究金屬矽化物對MOS結構中薄氧化層之緻密性的影響。吾人發現同時參雜多晶矽化物會導致薄氧化層之崩潰電壓下降，且在SiO2/Si介面形成較多的介面陷阱電荷，這是由於磷原子穿透到薄氧化層所造成。而離子佈值多晶矽化物在適當的退火條件下（800oC, 20 minutes furnace anneal），可以改善薄氧化層之緻密性，但在更高的退火時間及更長的退火溫度下會使薄氧化層之緻密性變差，這因為在熱處理過程中，參雜物會受熱的激化，擴散至薄氧化層中，增加薄氧化層之陷阱電荷，降低薄氧化層之緻密性。

Part 1
Effect of silicon surface micro-roughness and stress caused by hot DI water rinse on the electrical properties of deep-submicron CMOS transistors and MOS capacitors such as threshold voltage, saturation current, leakage current and breakdown voltage (VBD) and charge to breakdown (QBD) have been studied systematically. It shows that the hot DI water rinse can lead to micro-roughness causing the wider distribution of the saturation current as well as threshold voltage and degrading the breakdown voltage of devices. Additionally, increase of surface roughness could induce higher interface trap charge. The micro-roughness of silicon surface is evaluated by the atomic force microscope (AFM) while the density of interface trap charges is measured by the C-V measurement.

Part 2
The impact of different silicide technologies on the gate oxide integrity (GOI) in the metal-oxide-semiconductor (MOS) has been studied in detail. We found that the in situ doped polysilicon results in lower breakdown voltage and more interface trap charges due to the penetration of phosphorus atoms. The implant-polysilicon was found to improve the gate oxide integrity (GOI) under the 800oC, 20 minutes furnace anneal. But the GOI become worse for higher temperature and longer anneal time due to the thermal process caused dopants diffusing into the gate oxide film results in more traps in the oxide, then degrades the gate oxide integrity.

Part 1
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