成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	陳明新 Chen, Ming-Shing
論文名稱：	新穎金氧半電晶體奈米製程用於增進元件之特性及可靠性的研究 The Studies of Novel CMOS Nano Technologies to Promote Devices Performances and Reliability
指導教授：	方炎坤 Fang, Yean-Kuen
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 微電子工程研究所 Institute of Microelectronics
論文出版年：	2011
畢業學年度：	99
語文別：	中文
論文頁數：	80
中文關鍵詞：	製程技術、電晶體、微縮、閘極氧化層、應變工程、可靠性、超淺接面、快速回火
外文關鍵詞：	strain, USJ, finger pitch, cut off frequency, maximum oscillation frequency, CESL, dual-gate-oxide, tensile, compressive, Laser anneal, NBTI, RTP
相關次數：	點閱：129 下載：8
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

金氧半場效電晶體製程技術微縮進入奈米等級時，電晶體元件之性能已無法只靠單純的縮小閘極長度來提升。製程技術與物理極限上的種種限制，如曝光波長的影響、可靠度的考量、閘極氧化層太薄所導致嚴重的閘極漏電問題，都會增加金氧半場效電晶體向下微縮的困難。
為了增進元件性能，提昇載子的移動率，應變工程(Strain engineering)已漸成為先進元件開發的必要技術。本論文中對應變工程影響元件性能與可靠性做了更完整的探討。首度提出數種新的先進應變工程方法與材料，並研究它們對對元件特性行為之影響，諸如指狀閘極元件特性，可靠度變化與截止頻率與最大震動頻率之變化。
此外，本研究將吾人由實驗探討的先進應變工程(Strain engineering)配合TCAD模擬各種狀態下應力之變化，驗證其增進元件性能同時平衡NMOS及PMOS元件之特性。因為對互補式金氧半場效電晶體而言，所採用的先進應變工程方法必須能平衡NMOS及PMOS元件之特性，否則將會造成無法應用於IC電路設計或是增加製程複雜度的困擾。
最後，雷射退火(Laser anneal)應用於超淺接面工程(USJ)亦是奈米級先進電晶體元件開發必要技術之一，在此我們也提出雷射退火技術合併傳統快速回火(RTP)技術之最佳化製程，完全符合奈米級先進電晶體元件製程在元件性能上的需求，可同時達到元件最佳特性與可靠度特性。

In this dissertation, we study the impact of strain engineering and USJ (ultra shallow junction) technology by Laser anneal on nano meter scale MOSFETs performances in details. The study is divided into four parts: First, investigate the impact of CESL strain on device characteristic and reliability for CMOSFET , including (a) effects of the poly gate finger pitch on Ion , (b) hot carrier induced threshold voltage shift, (c) cut off frequency (fT) and maximum oscillation frequency(fmax) of the 40 nm n-channel MOSFETs with CESL strain and multi-finger gate structures.
Second, the impact of CESL strain on input/output (I/O) p-type MOSFETs under a dual-gate-oxide CMOS process. The process is fully compatible with conventional CMOS processing. The CESL strain (tensile / compressive ) induces Vth (threshold voltage) shift, which has become a crucial challenge in designing an advanced analog or mixed signal circuits.
Third, to investigate the latter strained silicon technology of SMT (stress-memory-technique) process, which meet the nMOSFET aggressive performance goal for new device node, but degrades the pMOSFET performance at the same time. In this work, mechanisms of pMOSFET degradation and improvement by SMT film optimization have been studied in details.
Finally, we investigated the USJ optimization by Laser anneal combining RTP anneal systematically. The origins of the obvious Vth shift (ΔVth ) in the 40 nm p-MOSFET with conventional RTP C-anneal for activation S/D implant dopant are investigated and attributed to the LSA deteriorated NBTI reliability.
By moving the RTP step to before the LSA step, the obvious VthH shift (ΔVth ) could be suppressed to almost same as the RTP only anneal. Best of all, the sequence change almost didn’t affect on the gain in driving current of the RTP/LSA C-anneal over the RTP only. Therefore, the developed method has the high potential for future deep nano CMOS technologies applications.

Contents : 
Abstract…I
Acknowledgments…V
Contents…VI
Table Captions…IX
Figure Captions…X

Chapter 1	Introduction…1
1-1    Background and Motivation…1
1-1-1  Strain engineering with the stressed contact etch stop layer (CESL)…2
1-1-2  Strain engineering with the stress-memory-technique (SMT)…3
1-1-3  USJ engineering with the optimization of Laser / RTP anneal sequence…4
1-2	Preface of this Dissertation…4

Chapter 2	Effect of Finger Pitch on the Driving Ability of a 40nm MOSFET with Contact Etch Stop Layer Strain in Multi-finger Gated Structure…7
2-1 	Introduction…7
2-2 	Experimental…8
2-3 	Results and discussions…10
2-4 	Conclusions…14

Chapter 3	Effect of Etch Stop Layer Stress on Negative Bias Temperature Instability of Deep Submicron p-type MOSFETs with Dual Gate Oxide…30
3-1	Introduction…30
3-2	Device Preparation and Measurements…31
3-3	Results and discussions…32
3-4	Conclusion…35

Chapter 4	Improvement of 40nm Low-Power PMOSFET Performances with the Optimized Blanket SMT Layer…46
4-1	Introduction…46
4-2	Experimental…47
4-3	Results and discussion…48
4-4	Conclusions…49

Chapter 5	A Novel Method to Improve Laser Anneal Worsened Negative Bias Temperature Instability in 40nm CMOS Technology…55
5-1	Introduction…55
5-2	Device fabrication and measurements	…56
5-3	Results and discussion…58
5-5	Conclusion…60

Chapter 6	Conclusions and Prospects…68
6-1	Conclusions…68
6-2	Prospects…69
6-2-1  High-k Gate Dielectric and Metal Gate Electrode…69
6-2-2  III-V Channels…70

Reference…72

Table Captions :
Table.4-I. PECVD with blanket SMT nitride layer split (SMT A-B-C-D)

Figure Captions :
Figure 2-1 The layout of a multi-finger gate structure with 5 fingers and 2
dummy poly gates.
Figure 2-2 TEM photos to show the cross section view of a multi finger gate structure with (a) wide pitch, and (b) narrow pitch.
Figure 2-3 The measured Ion as a function of finger pitch with CESL induced stress type as parameter. In region (I), the Ion decreases and increases with decreasing finger pitch under tensile stress and compressive stress, respectively. In region (II), the Ion increases for all stress types.
Figure 2-4 The model used to illustrate the change of the CESL stress into the channel for (a) wide pitch and (b) narrow pitch.
Figure 2-5 Effective mobility versus effective electric field for different poly finger pitches.
Figure 2-6 Threshold voltage (Vth) versus poly finger pitch for different poly finger widths (W)
Figure 2-7 Threshold-voltage shift (ΔVth) of n-channel MFGS MOSFETs with various poly finger pitches induced by HCI versus stress time for different CESL stress (a) tensile stress (b) compressive stress
Figure 2-8 The T-CAD simulated CESL caused stress amplitude in channel for (a) wide pitch, (b) narrow pitch.
Figure 2-9 The T-CAD simulated CESL caused stress distribution as a function of distance from the channel center with pitch width as parameter.
Figure 2-10 The T-CAD simulated CESL caused stress in channel as a function 	of poly finger pitch with CESL thickness as parameter for (a) tensile 	stress, and (b) compressive stress.
Figure 2-11 The plot of H21 vs. frequency characteristics of the MGFS NMOSFET (W=1µm and Nf=24)
Figure 2-12 The plot of Unilateral power gain (U) vs. frequency characteristics 	of the MGFS NMOSFET (W=1µm and Nf=24)
Figure 2-13 Cutoff frequency (fT with solid marks: ■, ▲…) and maximum 	oscillation frequency (fmax with empty marks: □, Δ …) of the 	MGFS NMOSFETs ( N=5 ) versus poly finger pitch for different 	poly finger width (W)
Figure 2-14 Cutoff frequency (fT with solid marks: ■, ▲ …) and maximum 	oscillation frequency (fmax with empty marks: □, Δ …) of the 	MGFS NMOSFETs (W =1µm) versus poly finger pitch for different 	poly finger number (N)
Figure 3-1 Brief process for dual-gate-oxide CMOS technology. Four steps (marked with stars) are harmful to the Gox interface.
Figure 3-2 Hydrogen content from FTIR measurement and stress for various CESL films. The inset (left) shows the FTIR spectra for various stresses.
Figure 3-3 ΔVth of a 3.3 V p-MOSFET with various CESL films measured after DC NBTI stress under 125ºC as a function of stress time in linear scale.
Figure 3-4 ΔVth of a 3.3 V p-MOSFET with various CESL films measured after DC NBTI stress under 125ºC as a function of stress time in log-log scale.  .
Figure 3-5 IDS vs channel length in dual-gate-oxide IO-nMOSFET with various types of CESL films.
Figure 3-6 Vth vs channel length in dual-gate-oxide IO-nMOSFET with various types of CESL films.
Figure 3-7 IDS vs channel length in dual-gate-oxide IO-pMOSFET with various types of CESL films.
Figure 3-8 Vth vs channel length in dual-gate-oxide IO-pMOSFET with various types of CESL films.
Figure 3-9 ΔVth vs stress time under the dynamic NBTI test for dual-gate-oxide I/O pMOSFET with various types of CESL films.
Figure 3-10 Schematic diagram to illustrate the retardation of the Si-H breaking and diffusion of H induced by the reacting force of the tensile stress in the CESL.
Figure 4-1 PMOS Ion-ioff is degraded around 8% compare to with and without SMT nitride layer and the insert plot shows the PMOS SIMS and Rsd to explain the performance degradation.
Figure 4-2 PMOS performance degradation compare to SMT nitride layer split hydrogen concentration after-anneal (SMT A-B-C-D)
Figure 4-3 Measured Nit and Vth shift (ΔVth ) (NBTI) for PMOS with, without SMT layer and sample A.
Figure 4-4 PMOS performance degradation and NMOS performance boost compare to SMT nitride layer split density(1/WER) [a.u.] (SMT A-B-C-D)
Figure 5-1 The key process sequence used for the fabrication of the nano MOSFET devices.
Figure 5-2 Scattering plot of the n-MOSFET devices with RTP only, Laser first (LSA→RTP) and RTP first (RTP→LSA) C-anneals. The Laser first (LSA→RTP) and RTP first (RTP→LSA) C-anneals get 6% and 5.5% gains over RTP only in Ion, respectively.
Figure 5-3 Scattering plot of the p-MOSFET devices with RTP only, Laser first (LSA→RTP) and RTP first (RTP→LSA) C-anneals. The Laser first (LSA→RTP) and RTP first (RTP→LSA) C-anneals get 2.8% and 2.3% gains over RTP only in Ion, respectively.
Figure 5-4 Vth shift (ΔVth ) for p-MOSFET with RTP only, Laser first (LSA→RTP) and RTP first (RTP→LSA) C-anneals.
Figure 5-5 Measured interface state density (Nit) by charge pumping measurements for p-MOSFET with RTP only, Laser first (LSA→RTP) and RTP first (RTP→LSA) C-anneals
Figure 5-6 Measured S/D extension sheet resistance (Rsd) for p-MOSFET with RTP only, Laser first (LSA→RTP) and RTP first (RTP→LSA) C-anneals.
Figure 5-7 Comparison of the secondary ion mass spectrometry (SIMS) dopant ion (Boron) profiles of a p-MOSFET after Laser first (LSA→RTP) and RTP first (RTP→LSA) C-anneals to the as implant.



                                    

【Reference】

[1] G. G. Shahidi, “Challenges of CMOS Scaling at below 0.1µm” The 12th International Conference on Microelectronics, pp. 5-8, 2000
[2] P. M. Zeitzoff, “MOSFET Scaling Trends and Challenges Through The End of The Roadmap” Proc. of IEEE Custom Integrated Circuit Conference, pp. 233-240, 2004.
[3] Y. Taur, “CMOS Scaling Beyond 0.1 µm: How Far Can It Go?” VLSI Symp. Tech. Dig., pp. 6-9, 1999.
[4] Y. C. Yeo, Q. Lu, W. C. Lee, T. J. King, C. Hu, X. Wang, X. Guo, and T. P. Ma, "Direct Tunneling Gate Leakage Current in Transistors with Ultrathin Silicon Nitride Gate Dielectric" IEE Electronic Letters, vol. 21, no. 11, pp. 540-542, 2000.
[5] S. Song, J. H. Yi, W. S. Kim, J. S. Lee, K. Fujihara, H. K. Kang, J. T. Moon, and M. Y. Lee, “CMOS Device Scaling Beyond 100nm” IEDM Tech. Dig., pp. 235-238, 2000.
[6] S. Song, W. S. Kim, J. S. Lee, T. H. Choe, J. H. Choi, M. S. Kang, U. I. Chung, N. I. Lee, K. Fujihara, H. K. Kang, S. I. Lee, and M. Y. Lee, “Design of Sub-l00nm CMOSFETs: Gate Dielectrics and Channel Engineeringv,” VLSI Symp. Tech. Dig., pp. 190-191, 2000
[7] T. Ghani, K. Mistry, P. Packan*, S. Thompson, M. Stealer*, S. Tyagi, M. Bohr, "Scaling Challenges and Device Design Requirements for High Performance Sub-50 nm Gate Length Planar CMOS Transistors," VLSI Symp. Tech. Dig., pp. 174-175, 2000.
[8] Y. C. Yeo, Q. Lu, W. C. Lee, T. J. King, and C. Hu, "Scaling Limit of Silicon Nitride Gate Dielectric for Future CMOS Technologies," Proc. of Device Research Conference, pp. 65-66, 2000.
[9] S. Yang, “High performance logic technology-scaling trend and future challenges,” Proc. ICSICT Tech. Dig., 2001, pp. 62-67.
[10] B. Yu, H. Wang, C. Riccobene, Q. Xiang, and M. R. Lin, "Limits of Gate-Oxide Scaling in Nano-Transistors," VLSI Symp. Tech. Dig., pp. 90-91, 2000.
[11] C. T. Lin, Y. K. Fang, W. K. Yeh, C. M. Lai, C. H. Hsu, L. W. Cheng and G. H. Ma, “Impacts of Notched-Gate Structure on Contact Etch Stop Layer (CESL) Stressed 90-nm nMOSFET,” IEEE Electron Device Lett., vol. 28, pp. 376-378, May. 2007.
[12] Y. J. Yang, M. H. Liao, C. W. Liu, Lingyen Yeh, T. L. Lee and M. S. Liang, “Superior n-MOSFET Performance by Optimal Stress Design,” in Semiconductor Device Research Symp., 2007, pp. 1-2.
[13] K. Ota, K. Sugihara, H. Sayama, T. Uchida, H. Oda, T. Eimori, H. Morimoto, and Y. Inoue, “Novel Locally Strained Channel Technique for High Performance 55 nm CMOS”, IEDM Tech. Dig., pp. 27–30, 2002.
[14] M. Goto, K. Tatsumura, S. Kawanaka, K. Nakajima, R. Ichihara, Y. Yoshimizu, H. Onoda, K. Nagatomo, T. Sasaki, T. Fukushima, A. Nomachi, S. Inumiya, H. Oguma, K. Miyashita, H. Harakawa, S. Inaba, T. Ishida, A. Azuma, T. Aoyama, M. Koyama, K. Eguchi, Y. Toyoshima, “Impact of Tantalum Composition in TaC/HfSiON Gate Stack on Device Performance of Aggressively Scaled CMOS Devices with SMT and trained CESL,” VLSI, pp: 132 – 133, 2008.
[15] V. P. Trivedi, G. S. Spencer, P. Grudowski, J. Liu, D. Sing, P. Choi, S. Parsons, V. Kolagunta and J. Cheek, “Performance Enhancement via Laser Anneal-Based RS/D Reduction in PD/SOICMOS,” in Int. SOI Conf., Niagara Falls, NY, 2006, pp. 21-22.
[16] A. Shima, Y. Wang, S. Talwar and A. Hiraiwa, “Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS,” in VLSI Symp. Tech. Dig., Honolulu, HI, 2004, pp. 174-175.
[17] S. K. H. Fung, H. T. Huang, S. M. Cheng, K. L. Cheng, S. W. Wang, Y. P. Wang, Y. Y. Yao, C. M. Chu, S. J. Yang, W. J. Liang, Y. K. Leung, C. C. Wu, C. Y. Lin, S. J. Chang, S. Y. Wu, C. F. Nieh, C. C. Chen, T. L. Lee, Y. Jin, S. C. Chen, L. T. Lin, Y. H. Chiu, H. J. Tao, C. Y. Fu, S. M. Jang, K. F. Yu, C. H. Wang, T. C. Ong, Y. C. See, C. H. Diaz, M. S. Liang and Y. C. Sun, “65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application,” in VLSI Symp. Tech. Dig., Honolulu, HI, 2004, pp. 92-93.
[18] Scott E. Thompson, Mark Armstrong, Chis Auth, Mohsen Alavi, Mark Buehler, Robert Chau, Steve Cea, Tahir Ghani, Glenn Glass, Thomas Hoffman, Chia-Hong Jan, Chis Kenyon, Jason Klaus, Kelly Kuhn, Zhiyong Ma, Brian Mcintyre, Kaizad Mistry, Anand Murthy, Borna Obradovic, Ramune Nagisetty, Phi Nguyen, Sam Sivakumar, Reaz Shaheed, Lucian Shifren, Bruce Tufts, Sunit Tyagi, Mark Bohr, and Youssef El-Mansy, “ A 90-nm Logic Technology Featuring Strained-Silicon” IEEE Trans. on Electron Devices, vol.51, no.11, pp.1790-1797, 2004.
[19] Claude Ortolland, Yasutoshi Okuno, Peter Verheyen, Christoph Kerner, Chris Stapelmann, Marc Aoulaiche, Naoto Horiguchi, and Thomas Hoffmann, “Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process “ IEEE TED, vol. 56, no. 8, pp.1690-1697, Aug. 2009.
[20] C. Ortolland, P. Morin, C. Chaton, E. Mastromatteo, C. Populaire, S. Orain, F. Leverd,P. Stolk, F. Boeuf & F. Arnaud, “Stress Memorization Technique (SMT) Optimization for 45nm CMOS,”VLSI technology 2006., pp. 78–79.
[21] P. Morin, F. Wacquant, M. Juhel, C. Laviron, D. Lenoble, “Influence of the spacer dielectric processes on PMOS junction properties”, Mater Sci. Eng., B 124-125, 2005, pp. 319.
[22] S. Severi, E. Augendre, S. Thirupapuliyur, K. Ahmed, S. Felch, V. Parihar , F. Nouri, T. Hoffman, T. Noda, B. O’Sullivan, J. Ramos, E. San Andrés, L. Pantisano, A. De Keersgieter, R. Schreutelkamp, D. Jennings, S. Mahapatra, V. Moroz, K. De Meyer, P. Absil, M. Jurczak and S. Biesemans, “Optimization of Sub-Melt Laser Anneal: Performance and Reliability,” in Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, 2006, pp. 1-4.
[23] R. Lindsay , B. Pawlak , J. Kittl , K. Henson , C. Torregiani , S. Giangrandi , R. Surdeanu , W. Vandervost , A. Mayur , J. Ross , S. McCoy , J. Gelpey , K. Elliott , X. Pages , A. Satta , A. Lauwers , P. Stolk and K. Maex "A comparison of spike, flash, SPER and laser annealing for 45 nm CMOS", in Proc. MRS Symp., vol. 765, 2003, pp. D7.4.1-D7.4.6.
[24] J-L. Everaert, E. Rosseel, C. Ortolland, M. Aoulaiche, T. Hoffmann, T. Pavelka and E. Don, “Control of laser induced interface traps with in-line corona charge metrology,” in IEEE Int. Conf. Advanced Thermal Processing of Semiconductors, Las Vegas, NV, 2008, pp. 163-168.
[25] E. Morifiji, H. S. Momose, T. Ohguro, T. Yoshitomi, H. Kimijima, F. Matsuoka, M. Kinugawa, Y. Katsumata and H. Iwai, “Future perspective and scaling down roadmap for RF CMOS,” in IEDM Tech. Dig., 1999, pp. 163-164.
[26] S. P. Voinigescu, S. W. Tarasewicz, T. MacElwee and J. Ilowski, “An Assessment of the State-of-the-Art 0.5μm Bulk CMOS Technology for RF Applications,” in IEDM Tech. Dig., 1995, pp. 721-724.
[27] Q. Huang, F. Piazza, P. Orsatti and T. Ohguro, “The Impact of Scaling Down to Deep-Submicron on CMOS RF Circuits,” IEEE J. Solid-St. Circ., vol. 33, pp. 1023-1036, Jul. 1998.
[28] H. Lee, J. H. Lee, Y. J. Park and H. S. Min, “Characterization Issues of Gate Geometry in Multifinger Structure for RF-SOI MOSFETs,” IEEE Electron Device Lett., vol. 23, pp. 288-290, May. 2002.
[29] C. C. Ho, C. W. Kuo, Y. J. Chan, W. Y. Lien and J. C. Guo, “0.13-μm RF CMOS and Varactors Performance Optimization by Multiple Gate Layouts,” IEEE Trans. Electron Device, vol. 51, pp. 2181-2185, Dec. 2004.
[30] C. Y. Chen, S. C. Chen, M. H. Tsai and S. H. Hsu “Wiring Effect optimization in 65nm low Power NMOS,” IEEE Electron Device Lett., vol. 29, pp.1245, Nov. 2008.
[31] M. Alam and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation”, Microelectron. Reliab., Vol. 45, no. 1, pp. 71-81, (2005).
[32] V. Reddy, A.T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishan, “ Impact of Negative Bias Temperature Instability on Digital Circuit Reliability, ” in Proc. International Reliability Physics Symposium, pp. 248-254, 2002.
[33] C. H. Liu, M. T. Lee, C. Y. Lin, J. Chen, K. Schruefer, J. Brighten, N. Rovedo, T. B. Hook, M. V. Khare, S. F. Huang, C. Wann, T. C. Chen, and T. H. Ning, “Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics,” in IEDM Tech. Dig., pp. 39.2.1-39.2.4, 2001.
[34] P. Chaparala, D. Brisbin and J. Shibley, “NBTI in dual gate oxide PMOSFETs”, Plasma and Process-Induced Damage, 2003, P. 138.
[35] T. B. Hook, E. Adler, F. Guarin, J. Lukaitis, N. Rovedo, and K. Schruefer, “The effects of fluorine on parametrics and reliability in a 0.18-mm 3.5/6.8 nm dual gate oxide CMOS technology,” IEEE Trans. Electron Device, Vol. 48, pp.1346-1353, 2001
[36] T. Sasaki, K. Kuwazawa, K. Tanaka, J. Kato, and D. L. Kwong, “Engineering of nitrogen profile in an ultrathin gate insulator to improve transistor performance and NBTI,” IEEE Trans. Electron Devices Lett., vol. 24, no. 3, pp. 150-152, 2003.
[37] S. J. Doh, H.-S. Jung, Y.-S. Kim, H.-J. Lim, J. P. Kim, J. H. Lee, J.-H. Lee, N.-I. Lee, H.-K. Kan, K.-P. Suh, S. G. Park, S. B. Kang, G. H. Choi, Y.-S. Chung, H.-S. Baikz, H.-S. Chang, M.-H. Cho, D.-W. Moon, H. B. Park, M. Cho, and C. S. Hwang, “Improvement of NBTI and electrical characteristics by ozone pre-treatment and PBTI issues in HfAlO(N) high-k gate dielectrics,” in IEDM Tech. Dig., 2003, P. 38.7.1.
[38] T. Kawae, Y. Minemura, S. Fukuda, T. Hirano, Y. Suzuki, M. Saito, S. Kadomura, and S. Samukawa, “Drastically Improved NBTI Lifetime By Periodic Plasma Nitridation for 90nm Mobile Applications at Low Voltage Operation,”: International Workshop on Gate Insulator, 2003, P. 146.
[39] M. A. Alam, “A critical examination of the mechanics of dynamic NBTI for PMOSFETs,” in IEDM Tech. Dig., 2003, pp. 14.4.1–14.4.4.
[40] H. R. Rhee, H. Lee, T. Ueno, D. S. Shin, S. H. Lee, Y. Kim, A. Samoilov, P. O. Hansson, M. Kim, H. S. Kim, and N. I. Lee, “Negative Bias Temperature Instability of Carrier-Transport Enhanced pMOSFET with Performance Boosters,” in IEDM Tech. Dig., 2005, pp. 692-695.
[41] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. Mansy, “ A 90-nm Logic Technology Featuring Strained-Silicon”, IEEE Trans. on Electron Devices, vol.51, no.11, pp.1790-1797, 2004.
[42] K. O. Jeppson, C. M. Svensson, "Negative bias stress of MOS devices at high electric fields and degradation of MOS devices", J. Appl. Phys., vol.48, pp.2004-2014, 1977.
[43] T. F. Yen, C. M. Chiu and K. F. Chiu, “Photo-resist trimming for sub 0.1 μm generation integrated circuit devices by Cl2/O2 transform coupled plasma,” Microelectron. Eng., vol. 75, no. 2, pp. 201-209, Aug. 2004.
[44] B. J. Pawlak, T. Janssens, T. Brijs, W. Vandervosrt, E. J. H. Collart, S. B. Felch and N. E. B. Cowern, “Effect of amorphization and carbon co-doping on activation and diffusion of boron in silicon,” Appl. Phys. Lett., vol. 89, no. 6, pp. 062110, Aug. 2006.
[45] H. Graoui, M. Foad and V. Moroz, “Source and Drain Extension Formation Using Carbon Co-implantation for PMOS Devices,” in Proc. Ultra-Shallow Junctions, 2005, pp. 346.
[46] A. Pouydebasque, B. Dumont, S. Denorme, F. Wacquant, M. Bidaud, C. Laviron, A. Halimaoui, C. Chaton, J. D. Chapon, P. Gouraud, F. Leverd, H. Bernard, S. Warrick, D. Delille, K. Romanjek, R. Gwoziecki, N. Planes, S. Vadot, I. Pouilloux, F. Arnaud, F. Boeuf and T. Skotnicki, “High density and high speed SRAM bit-cells and ring oscillators due to laser annealing for 45nm bulk CMOS,” in Int. Electron Devices Meeting Tech. Dig., Washington, DC, 2005, pp. 663-666.
[47] T. Yamamoto, T. Kubo, T. Sukegawa, K. Hashimoto and M. Kase, “Advanced Junction Profile Engineering Featuring Laser Spike Annealing and Co-Implantation for Sub-30-nm Strained CMOS Devices,” in VLSI Symp. Tech. Dig., Honolulu, HI, 2006, pp. 186-187.
[48] G. Groeseneken, H. E. Maes, N. Bertran and R. F. De Keersmaecker, “A Reliable Approach to Charge-Pumping Measurements in MOS Transistors,” IEEE Trans. Electron Devices, vol. 31, no. 1, pp. 42-53, 1984.
[49] Taniguchi K.; Tanaka M.; Hamaguchi C.; Imai K. “Density relaxation of silicon dioxide on (100) silicon during thermal annealing,” J. Appl. Phys., vol. 67, no. 5, pp. 2195-2198, Mar. 1990.
[50] A. Stesmans, “Structural relaxation of Pb defects at the (111) Si-SiO2 interface as a function of oxidation temperature: the Pb-generation-stress relationship,” Phys. Rev. B, vol. 48, no. 4, pp. 2418-2435, Jul. 1993.
[51] N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, “Estimation of the Effects of Remote Charge Scattering on Electron Mobility of n-MOSFET’s with Ultrathin Gate Oxides,” IEEE Trans. Electron Devices, vol. 47, no. 2, pp. 440-447, 2000.
[52] M. Kadoshima, Y. Sugita, K. Shiraishi, H. Watanabe, A. Ohta, S. Miyazaki, K. Nakajima, T. Chikyow, K. Yamada, T. Aminaka, E. Kurosawa, T. Matsuki, T. Aoyama, Y. Nara, Y. Ohji, ”Fermi-level pinning position modulation by Al-containing metal gate for cost-effective dual-metal/dual-high-k CMOS" VLSI Symp. Tech. Dig., pp. 66-67, 2007.
[53] P. Sivasubramani, T. S. Böscke, J. Huang, C. D.Young, P. D. Kirsch, S. A. Krishnan, M. A. Quevedo-Lopez, S. Govindarajan, B. S. Ju, H. R. Harris, D. J. Lichtenwalner, J. S. Jur, A. I. Kingon, J. Kim, B. E. Gnade, R. M. Wallace, G. Bersuker, B. H. Lee, and R. Jammy” Dipole Moment Model Explaining nFET Vth Tuning Utilizing La, Sc, Er, and Sr Doped HfSiON Dielectrics" VLSI Symp. Tech. Dig., pp. 68-69, 2007.
[54] K. Iwamoto, A. Ogawa, Y. Kamimuta, Y. Watanabe, W. Mizubayashi, S. Migita, Y. Morita, M. Takahashi, H. Ito, H. Ota, T. Nabatame, and A. Toriumi,”Re-examination of Flat-Band Voltage Shift for High-k MOS Devices” VLSI Symp. Tech. Dig., pp. 70-71, 2007.
[55] K. Akiyama, W. Wang, W. Mizubayashi, M. Ikeda, H. Ota, T. Nabatame and A. Toriumi ,”VFB Roll-off in HfO2 Gate Stack after High Temperature Annealing Process - A Crucial Role of Out-diffused Oxygen from HfO2 to Si –“VLSI Symp. Tech. Dig., pp. 72-73, 2007.
[56] S. Inumiya, Y. Akasaka, T. matsuki, F. Ootsuka, K. Torii, and Y. Nara, “A Thermally-Stable Sub-0.9nm EOT TaSix/HfSiON Gate Stack with High Electron Mobility, Suitable for Gate-First Fabrication of hp45 LOP Devices,” IEDM Tech. Dig., pp. 23-26, 2005.
[57] Y. T. Hou, F. Y. Yen, P. F. Hsu, V. S. Chang, P. S. Lim, C. L. Hung, L. G. Yao, J. C. Jiang, H. J. Lin, Y. Jin, S. M. Jang, H. J. Tao, S. C. Chen and M. S. Liang, “High Performance Tantalum Carbide Metal Gate Stacks for nMOSFET Application,” IEDM Tech. Dig., pp. 31-34, 2005.
[58] R. I. Hegde, D. H. Triyoso, P. J. Tobin, S. Kalpat, M. E. Ramon, H.-H. Tseng, J. K. Schaeffer, E. Luckowski, W. J. Taylor, C. C. Capasso, D. C. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L. B. La, E. Hebert, R. Cotton, X-D. Wang, S. Zollner, R. Gregory, D. Werho, R. S. Rai, L. Fonseca, M. Stoker, C. Tracy, B. W. Chan*, Y. H. Chiu*, and B. E. White Jr. “Microstructure Modified HfO2 Using Zr Addition with TaxCy Gate for Improved Device Performance and Reliability,” IEDM Tech. Dig., pp. 35-38, 2005.
[59] R. Jha, B. Lee, B. Chen, S. Novak, P. Majhi1 ,and V. Misra, “Dependence of PMOS Metal Work Functions on Surface Conditions of High-K Gate Dielectrics,” IEDM Tech. Dig., pp. 43-46, 2005.
[60] R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalierous, A. Majumdar, M. Metz, and M. Radosavljevic, “Benchmarking nanotechnology for high-performance and low-power logic transistor applications,” IEEE Transcations On Nanotechnology, vol. 4, no. 2, Mar. 2005.
[61] D. H. Kim and J. A. del Alamo, "30 nm E-mode InAs PHEMTs for THz and future logic applications," in Tech. Dig. - Int. Electron Devices Meet., 2008, pp. 719-722.
[62] Y. Sun, E. W. Kiewra, J. P. de Souza, J. J. Bucchignano, K. E. Fogel, D. K. Sadana, and G. G. Shahidi, "Scaling of In0.7Ga0.3As buried-channel MOSFETs," in Tech. Dig. - Int. Electron Devices Meet., 2008, pp. 367-370.
[63] M. Passlack, M. Hong, J. P. Mannaerts, S. N. G. Chu, R. L. Opila, and N. Moriya,“In-Situ Ga2O3 Process for GaAs Inversion/Accumulation Device and SurfacePassivation Applications,” Tech. Dig.- Int. Electron Devices Meet. 1995, pp. 383.
[64] H. C. Chin, M. Zhu, Z. C. Lee, X. Liu, K. M. Tan, H. K. Lee, L. Shi, L. J. Tang, C. H. Tung, G. Q. Lo, L. S. Tan, and Y. C. Yeo,“A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel GaAs n-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stack," in IEDM Tech. Dig., pp. 383-386, 2008.
[65] Y. Xuan, T. Shen, M. Xu, Y.Q. Wu, and P. D. Ye, “High-performance Surface Channel In-rich In0.75Ga0.25As MOSFETs with ALD High-κ as Gate Dielectric,” IEDM Tech. Dig., p. 371. 2008.
[66] S. Suthram, Y. Sun, P. Majhi, I. Ok, H. Kim, H. R. Harris, N. Goel, S. Parthasarathy, A. Koehler, T. Acosta, T. Nishida, H. H. Tseng, W. Tsai, J. Lee, R. Jammy, and S. E. Thompson, “Strain additivity in III-V channels for CMOSFETs beyond 22 nm technology node,” in VLSI Symp. Tech. Dig., 2008, pp. 182–183.

校內：2012-07-11公開
校外：2012-07-11公開

簡易檢索 / 詳目顯示

相關論文