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研究生： 陳思宏
Chen, Shih-Hong
論文名稱： 具有抵抗製程電壓溫度變異之電流式數位至類比轉換器與跳躍式視窗的分段逐漸趨近式類比至數位轉換器之設計
Design of Sub-Ranging SAR ADC with PVT-Stabilized Current DAC and Bypass Window
指導教授： 鄭光偉
Cheng, Kuang-Wei
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年： 2019
畢業學年度： 107
語文別： 英文
論文頁數： 148
中文關鍵詞： 逐漸趨近式 、跳躍式視窗 、時間數位轉換器 、抗製程電壓溫度變異 、電流式數位類比轉換器 、數位類比轉換器
外文關鍵詞： successive approximation, skipping window, TDC, PVT-stabilization, current DAC, analog-to-digital converter
相關次數： 點閱：130  下載：6 
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    • 本論文提出了三個應用於高解析度及高能量轉換效率的逐漸趨近式類比至數位轉換器的電路技術。首先，分別實現利用時間特性及利用電壓特性兩種方式建立跳躍式視窗來節省電容陣列切換的機制，並改善線性度。第二，低漏電的架構調整及設計可以提高準確度。第三，在最後的兩個位元轉換步驟，以一個具有抵抗製程電壓溫度變異的電流式數位至類比轉換器來取代原本使用的電容陣列組成的數位至類比轉換器，以減少整體電容數目。除此之外，低雜訊的比較器及低抖動時間取樣的設計也呈現在本論文中。
    本論文呈現兩個實做晶片。第一個設計採用時間特性的跳躍式視窗及搭配滴漏電架構。使用台積電65奈米製程，其核心電路的面積為0.169 mm^2。此電路在0.6伏特的電壓供應下操作在10萬赫茲的取樣頻率(100-kS/s)。實測效能顯示，在奈奎斯特輸入頻率下，其有效位元為10.29 位元 (SNDR為63.71 dB)，得到的轉換效率分別為11.18 fJ/conv.-step與169.24 dB。
    第二個設計採用電壓特性的跳躍式視窗及搭配具有抵抗製程電壓溫度變異的電流式數位至類比轉換器。使用台積電90奈米製程。其核心電路的面積為0.173 mm^2。此電路在0.8伏特的電壓供應下操作在100萬赫茲的取樣頻率(1-MS/s)。實測效能顯示，在奈奎斯特輸入頻率下，其有效位元為10.35 位元 (SNDR為64.04 dB)，得到的轉換效率分別12.51 fJ/conv.-step與168.9 dB。

    This dissertation proposes three techniques for high resolution SAR ADC with high power efficiency. First, both time domain and voltage domain skipping window are realized to save the power consumption of capacitive DAC and to improve the linearity. Second, low leakage design adjustment is taken into consideration to increase the accuracy. Third, a PVT-stabilized current DAC is implemented to replace the two LSB capacitors to reduce the numbers of total capacitors. In addition, low noise design for the comparator and low clock jitter edge for the sampling are also presented.
    There are two implemented proof-of-concept prototypes. The first one adopts a time domain skipping window and low leakage design adjustment. It is fabricated in TSMC 65-nm CMOS process with the core area of 0.169 mm^2. It operates at 100-kS/s with 0.6 V supply voltage. The measurement results show that the prototype ADC achieves 63.71 dB SNDR with a Nyquist rate input. The resultant FoMW and FoMS of the prototype are 11.18 fJ/conv.-step and 169.24 dB, respectively.
    The second one adopts a voltage domain skipping window and a PVT-stabilized current DAC. It is fabricated in TSMC 90-nm CMOS process with core area of 0.173 mm^2. The measurement results show that the prototype ADC achieves 66.04 dB SNDR with a Nyquist rate input. The resultant FoMW and FoMS of the prototype are 12.51 fJ/conv.-step and 168.9 dB, respectively.

    Abstract III 誌謝 V Table of Contents VII List of Tables X List of Figures XI Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization 5 Chapter 2 Fundamentals of Analog-to-Digital Converters 6 2.1 Introduction 6 2.2 Ideal A/D converter 7 2.3 Quantization Error 8 2.4 Static Specification 11 2.4.1 Offset error 12 2.4.2 Gain error 13 2.4.3 Differential Nonlinearity (DNL) 14 2.4.4 Integral Nonlinearity (INL) 15 2.4.5 Monotonicity 17 2.4.6 Static Testing Methods 18 2.5 Dynamic Specification 20 2.5.1 Signal-to-Noise Ratio (SNR) 21 2.5.2 Signal-to-Noise and Distortion Ratio (SNDR) 22 2.5.3 Effective Number of Bits (ENOB) 22 2.5.4 Spurious-Free Dynamic Range (SFDR) 23 2.5.5 Total Harmonic Distortion (THD) 23 2.5.6 Effect Resolution Bandwidth (ERBW) 24 2.5.7 Dynamic Range (DR) 25 2.5.8 Figure of Merit (FoM) 25 Chapter 3 Literature Review 27 3.1 Capacitor Switching Methods 27 3.1.1 Monotonic Switching Method [11] 29 3.1.2 Merged Capacitor Switching Method 31 3.1.3 Switchback Switching Method 33 3.1.4 Split-Monotonic Switching Method 35 3.2 Analysis among Comparators 37 3.2.1 Latch-Type Comparator 38 3.2.2 Two-Stage Comparator 39 3.2.3 Time-domain Comparator 40 3.2.4 Improved by Architecture 40 3.2.5 Summary 42 3.3 High Resolution Method 42 3.3.1 Calibration 42 3.3.2 Two-stage Method 44 3.3.3 Noise Shaping SAR 46 Chapter 4 A 12-bit 100-kS/s SAR ADC with Time Domain Skipping Logic 48 4.1 Abstract 48 4.2 The Proposed Techniques 49 4.2.1 Skipping Logic 49 4.2.2 Low Leakage Design 56 4.3 Architecture of the Proposed SAR ADC 59 4.4 Key Circuit Building Blocks 60 4.4.1 Bootstrapped Switch 60 4.4.2 Dynamic Comparator 65 4.4.3 Time Domain Window Generator 71 4.4.4 SAR Control Logic and Digital Error Correction 76 4.4.5 Capacitor Array 78 4.5 Noise Budget 82 4.6 Simulation and Measurement Results 86 4.6.1 Floor Plan and Layout 87 4.6.2 Simulation Results 88 4.6.3 Measurement Setup 93 4.6.4 Measurement Results 95 Chapter 5 A 12-bit 1-MS/s SAR ADC Sub-Ranged with PVT-Stabilized Current DAC 100 5.1 Abstract 100 5.2 The Proposed Techniques 101 5.2.1 Skipping Logic 101 5.2.2 PVT-Stabilization Current DAC 103 5.3 Architecture of the Proposed SAR ADC 109 5.4 Key Circuit Building Blocks 111 5.4.1 Bootstrapped Switch 111 5.4.2 Dynamic Comparator 113 5.4.3 PVT-stabilization Current DAC 114 5.4.4 SAR Control Logic and Digital Error Correction 119 5.4.5 Capacitive Array 120 5.5 Noise Budget 123 5.6 Simulation and Measurement Results 124 5.6.1 Floor Plan and Layout 124 5.6.2 Simulation Results 126 5.6.3 Measurement Setup 132 5.6.4 Measurement Results 134 Chapter 6 Conclusions and Future Work 140 6.1 Conclusions 140 6.2 Future Work 141 Reference 143

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