在57~64-GHz毫米波頻段中，目前雖然尚未定義確切的系統規範，但是全世界各家大廠均已經在積極整合相關60-GHz毫米波積體電路。本篇論文主要考量低功率與低相位雜訊之特性，利用較為成熟0.18-um製程技術進行27-GHz壓控振盪器的設計。在未來搭配一個倍頻器的情況下可以提供一個54-GHz的訊號源。
透過國家晶片系統設計中心(CIC)的細心量測之下，測得振盪頻率為26.96~ 27.95-GHz，可調頻率範圍約1-GHz。在供應電壓為1.8V時，消耗功率為3.5mW；輸出功率為-7.88 dBm；在27-GHz量測到的相位雜訊為-99.39 dBc/Hz@1MHz offset和-120.94 dBc/Hz@10MHz offset；FOM指數為-182.56 dBc (@1MHz offset) ~ -184.11 dBc (@10MHz offset)之間；晶片面積大小為0.855*0.679 mm2。
本篇論文實現之晶片在相位雜訊與模擬之間有些許差異，電感以EM模擬後比較量測值相去不遠，預計未來對晶片內之走線、電感與電容進行EM模擬，以達到更精確之模擬結果，並將技術轉移到如90-nm CMOS先進製程之中，期望未來能達到低功率、高效能的整合目標。

Though the system standards for the applications in the V-band of 57 to 64 GHz are still not clear, the main leadership design companies have already put a great effort on the integration of 60-GHz mm-wave front-end circuits. In this thesis, a 27-GHz voltage-controlled oscillator (VCO) with low power and low phase-noise performances are designed in a mature 0.18-um CMOS process. This oscillator can provide a 54-GHz signal in the case with the help of a frequency doubler.
From the measurement results measured by CIC, the output frequency of the VCO ranging from 26.96 to 27.95 GHz (with a tuning range of about 1 GHz). The total power consumption is 3.5 mW from a 1.8V supply voltage. The output power is -7.88 dBm. The measured phase noise at 27 GHz is -99.39 dBc/Hz @ 1MHz offset and -120.94 dBc/Hz@10 MHz offset. The calculated figure-of-merits (FOM) are about in the range of -182.56 dBc (at 1 MHz offset) and -184.11 dBc (at 10 MHz offset). The chip size is about 0.855x0.679 mm2.
It is shown that there are some inconsistences between the measurement and simulation results of phase noise. After EM simulation of inductor, it found the result is similar to measurement. In the future, for the more precise simulation results, the layout of inter connection lines, inductors, and capacitances have to be taken into the design. Simultaneously, we would like to transfer this design from a 0.18um CMOS to a 90nm CMOS process, in order to achieve the lower power and higher performance.

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