| 研究生: |
彭勝賢 Peng, Sheng-Shian |
|---|---|
| 論文名稱: |
基於混合主記憶體之負載平衡機制設計與實作 Design and Implementation of a Load Balancing Mechanism for Hybrid Main Memories |
| 指導教授: |
張大緯
Chang, Da-Wei |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年: | 2017 |
| 畢業學年度: | 106 |
| 語文別: | 英文 |
| 論文頁數: | 40 |
| 中文關鍵詞: | 混合記憶體 、負載平衡 、效能 、相變化記憶體 |
| 外文關鍵詞: | Hybrid memory, Load balancing, Performance, PCM |
| 相關次數: | 點閱:54 下載:0 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
為了增加系統主記憶體的容量,相變化記憶體近年來已經發展成一個有前途的技術。不像其他的非揮發性記憶體,例如: 快閃記憶體,相變化記憶體具有位元組定址的能力而且它的存取時間是座落在奈秒等級。因此,適合使用相變化記憶體當作系統主記憶體並且在未來有可能會取代動態隨機存取記憶體。然而,相變化記憶體因為有一些嚴重的缺陷導致相變化記憶體現在還無法直接取代動態隨機存取記憶體。無論是存取的時間或是存取的耗能,相變化記憶體都是高於動態隨機存取記憶體,而且相變化記憶體還有寫入限制的問題。為了解決這些問題和利用雙方記憶體的優點,結合小容量動態隨機存取記憶體和大容量相變化記憶體的混合記憶體系統就被提了出來。
在此篇論文中,我們在混合記憶體系統提出一個新的頁面放置方法叫做Hybrid memory balancer (Hymemba),它能夠有效降低記憶體請求的排隊延遲進而提升整體系統的記憶體存取時間。我們修改記憶體控制器來達到紀錄頁面的記憶體存取資訊、觀察雙方記憶體控制器的負載程度和每隔一段時間動態地從高負載的記憶體控制器搬移頁面到低負載的記憶體控制器。
實驗顯示Hymemba與對照組[17]相比,平均記憶體存取時間可以改善最多78% (平均53%),並且動態地搬移成本最多只有0.79%。在能量消耗方面,雖然Hymemba為了效能會將一些熱的資料搬移置相變化記憶體,但是整體的耗能是接近的。
Phase change memory (PCM) has become a promising technology to increase the capacity of main memory in recent years. Unlike other non-volatile memories, i.e. Flash , PCM is byte-addressable and the access time of PCM is in nanosecond range. Therefore, PCM is appropriate for main memory and has potential to replace DRAM in the future. Nevertheless, PCM has some critical drawbacks making PCM cannot directly substitute for DRAM at once. The access time and energy of PCM are higher than DRAM and PCM has limited endurance. To resolve these problems and take merits of both memory systems, hybrid memory systems which combine a small DRAM and a large PCM are proposed.
In this paper, we proposed a new page placement mechanism called Hybrid memory balancer (Hymemba) that reduces queueing delay of memory requests to improve the overall memory access latency in hybrid memory systems. We modify the memory controller to record memory access information of pages, observe the load of both controllers and dynamically migrate pages from the overloading controller to the other one periodically.
Evaluation results show that Hymemba can improve the average memory access latency by up to 78% (53% on average) relative to RBLA-Dyn and the dynamic migration overhead is only up to 0.79%. Moreover, the total energy consumption is close to competitor within 3% although Hymemba allocates some hot pages to PCM for performance.
[1] The International Technology Roadmap for Semiconductors. Process integration, devices, and structures, 2010.
[2] S. Raoux et al., “Phase-change random access memory: A scalable technology,” IBM Journal of Research and Development, vol. 52, no. 4/5, pp. 465–479, 2008.
[3] J.A. Mandelman, R.H. Bennard, G.B Bronner, J.K. DeBrosse, R. Divakaruni, Y. Li and C.J. Radens, “Challenges and Future Directions for the Scaling of Dynamic Random-Access Memory (DRAM),” IBM Journal of Research and Development, vol. 46, no. 2/3, pp. 187-212, 2002.
[4] U. Hoelzle and L. A. Barroso, The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines, 1st ed. San Mateo, CA, USA: Morgan Kaufmann, 2009.
[5] C. Lefurgy et al., “Energy Management for Commercial Servers,” Computer, Dec. 2003, pp. 39-47.
[6] The ITRS Working Group (2007). International Technology Roadmap for Semiconductors, Emerging Research Devices.
[7] S. Eilert, M. Leinwander, and G. Crisenza, “Phase change memory: A new memory technology to enable new memory usage models,” in Proc. 1st IEEE Int. Memory Workshop (IMW’09), 2009, pp. 1–2.
[8] N. H. Seong, D. H. Woo, and H. S. Lee, “Security refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping,” in Proc. 37th Int. Symp. Comput. Archit. (ISCA’10), 2010, pp. 383–394.
[9] P. Zhou, B. Zhao, J. Yang, and Y. Zhang, “A durable and energy efficient main memory using phase change memory technology,” in Proc. 36th Int. Symp. Comput. Archit. (ISCA’09), 2009, pp. 14–23.
[10] M. K. Qureshi, V. Srinivasan, and J. A. Rivers, “Scalable high performance main memory system using phase-change memory technology,” in Proc. 36th Int. Symp. Comput. Archit. (ISCA’09), 2009, pp. 24–33.
[11] G. Dhiman, R. Ayoub, and T. Rosing, “PDRAM: A hybrid PRAM and DRAM main memory system,” in Proc. 46th ACM/IEEE Des. Autom. Conf. (DAC’09), 2009, pp. 664–669.
[12] B. C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger, “Phase-change technology and the future of main memory,” IEEE Micro, vol. 30, no. 1, pp. 143–143, 2010.
[13] B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, “Architecting Phase Change Memory as a Scalable DRAM Alternative,” in Proceedings of the 36th International Symposium on Computer Architecture, 2009, pp. 2–13.
[14] J. L. Henning, “Performance Counters and Development of SPEC CPU2006,” Computer Architecture News, vol. 35, no. 1, 2007.
[15] R. M. Hollander and P. V. Bolotoff, “Ramspeed, a cache and memory benchmarking tool”, November 2002.
[16] C. Bienia, S. Kumar, J. P. Singh, and K. Li, “The PARSEC Benchmark Suite: Characterization and Architectural Implications,” in Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, October 2008.
[17] H. Yoon, J. Meza, R. Ausavarungnirun, R. A. Harding, and O. Mutlu, “Row buffer locality aware caching policies for hybrid memories,” in Proc. IEEE 30th Int. Conf. Comput. Des., 2012, pp. 337–344.
[18] S. Lee, H. Bahn, and S. H. Noh, “CLOCK-DWF: A write-historyaware page replacement algorithm for hybrid PCM and DRAM memory architectures,” IEEE Trans. Comput., vol. 63, no. 9, pp. 2187–2200, Sep. 2014.
[19] H. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, “Phase change memory,” Proc. IEEE, vol. 98, no. 12, pp. 2201–2227, Dec. 2010.
[20] Micron. 1Gb DDR2 SDRAM Component: MT47H128M8HQ-25, May 2007. http://download.micron.com/pdf/datasheets/dram/ddr2/1GbDDR2.pdf.
[21] K. H. Park et al., “Efficient Memory Management of a Hierarchical and a Hybrid Main Memory for MN-MATE Platform,” in PMAM, 2012, pp. 83-92
[22] L. Ramos et al., “Page Placement in Hybrid Memory Systems,” in ICS, 2011, pp. 85-95
[23] R. Salkhordeh and H. Asadi, “An Operating System level data migration scheme in hybrid DRAM-NVM memory architecture,” in DATE, 2016, pp. 936-941
[24] Z. Wu et al., “APP-LRU: A new page replacement method for PCM/DRAM-based hybrid memory systems,” in NPC, 2014, pp.84-95.
[25] Y. Zhou, J. F. Philbin, and K. Li., “The multi-queue replacement algorithm for second level buffer caches,” in Proceedings of the Usenix Technical Conference, 2001, pp. 91-104.
[26] N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood, “The GEM5 Simulator,” SIGARCH Computer Architecture News, vol. 39, no. 2, May 2011.
校內:2022-11-21公開