旋轉力矩轉移磁阻式隨機存取記憶體 (Spin-transfer torque magnetic RAM, STTMRAM)是目前一款備受看好的記憶體技術。其使用磁性穿隧接面 (Magnetic Tunnel Junction, MTJ)來存儲二進制資料。STT-MRAM具備多項優點，例如：低漏電功耗，高密度，高耐寫性和非揮發性，使其很適合運用於快取記憶體 (Cache)或主記憶體 (Main Memory)中。與此同時，隨著CMOS製程技術的發展，在電路可靠性方面，偏壓溫度不穩定性 (Bias Temperature Instability, BTI)效應已成為一個首要的議題。BTI效應會導致CMOS電晶體的臨界電壓上升，減弱CMOS電晶體的導電性能，增加感測放大器 (Sense amplifier)的感測延遲 (Sensing delay)。STT-MRAM的感測放大器在讀到“0”和“1”時，其遭受的BTI所導致的老化 (Aging)是不一樣的。其讀到“0”遭受到BTI效應的影響會比讀到“1”時來得大。若感測放大器常讀到“0”的話，其遭受BTI效應的影響又會更大。這會連帶導致感測放大器的老化和感測延遲變得更加嚴重。本論文研究BTI效應對STT-MRAM感測放大器的影響，提出多數決技術和交替感測技術，以減少感測放大器讀取到“0”的次數來減緩BTI效應對電路老化。多數決技術會依據過去寫入資料數值的多數性 (Majority), 以適量地翻轉將要被寫入的資料。在交替感測技術中，每個Cache Way的感測放大器可以與另一個的Cache Way的感測放大器來輪流感測資料。其目的主要是用來平均分攤這兩個Cache Way的感測放大器讀到“0”的次數，以便減少老化。為了減少老化造成的延遲增加，本篇論文使用正向基底偏壓 (Forward Body Bias)技術，而減小CMOS電晶體的臨界電壓，使其導電效能變好。在實驗結果的部分，同時使用三個所提出的技術能減少29.93% 的讀到“0”的延遲和57.67% 的讀到“1”的延遲。

Spin-transfer torque magnetic RAM (STT-MRAM), which uses magnetic tunnel junction (MTJ) to store binary data, is a promising memory technology. With many benefits such as low leakage power, high density, high endurance, and non-volatility, it has been explored as SRAM replacement for cache design or DRAM replacement for main memory. Meanwhile, with the continuous shrinking of CMOS process technology, the bias temperature instability (BTI) effect has become a major reliability issue. The BTI effect increases the threshold voltage of the CMOS transistor, reduces the driving current of the CMOS transistor, and exacerbates the sensing delay of the sense amplifier. The STT-MRAM sense amplifier suffers from different BTI-induced degradation while reading 0s and reading 1s, and the degradation in reading 0s is larger than that in reading 1s. If the STT-MRAM sense amplifier often senses 0s, it will suffer a larger BTI effect. This larger BTI effect exacerbates the sensing delay of the sense amplifier. This work investigates the BTI effect on the STT-MRAM sense amplifier, and proposes a majority-based technique and an alternative sensing technique to reduce degradation by reducing the number of reading 0s. The proposed majority-based technique adaptively flips the data before writing the data to the STT-MRAM data array. In the proposed alternative sensing technique, the sense amplifiers of a cache way can alternatively sense the data with the sense amplifiers of another cache way and balances the number of reading 0s between the sense amplifiers of two cache ways. To further improve the sense delay, we use forward body bias on the NMOS access transistor because the forward body bias can reduce the threshold voltage of the CMOS transistor and increase the driving current of the CMOS transistor. Experimental results show that using the three proposed techniques simultaneously can improve the sensing delay of reading 0s and reading 1s 29.93% and 57.67% on average, respectively.

[1] Synopsys Design Compiler. https://www.synopsys.com/implementation-and-signoff/rtl-synthesis-test.html.
[2] I. Agbo, M. Taouil, S. Hamdioui, H. Kukner, P. Weckx, P. Raghavan, and F. Catthoor. Integral Impact of BTI and Voltage Temperature Variation on SRAM Sense Amplifier. In VLSI Test Symposium (VTS), pages 1–6, 2015.
[3] P. K. Amiri, Z. M. Zeng, J. Langer, H. Zhao, G. Rowlands, Y. J. Chen, I. N. Krivorotov, J. P. Wang, H. W. Jiang, J. A. Katine, Y. Huai, K. Galatsis, and K. L. Wang. Switching current reduction using perpendicular anisotropy in cofeb-mgo magnetic tunnel junctions. Applied Physis Letter (AIP), 98(11):112 507–112 507–3, March 2011.
[4] H. Amrouch, V. M. van Santen, T. Ebi, V. Wenzel, and J. Henkel. Towards interdependencies of aging mechanisms. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 478–486, 2014.
[5] D. Apalkov, A. Khvalkovskiy, S. Watts, V. Nikitin, X. Tang, D. Lottis, K. Moon, X. Luo, E. Chen, A. Ong, A. Driskill-Smith, and M. Krounbi. Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). ACM Journal on Emerging Technologies in Computing Systems (JETC), 9(2), 2013.
[6] F. Cacho, A. Cros, X. Federspiel, V. Huard, and C. Roma. Bti induced dispersion: Challenges and opportunities for sram bit cell optimization. In IEEE International Reliability Physics Symposium (IRPS), pages 7C–1–1–7C–1–6, April 2016.
[7] Y. Cao and W. Zhao. Predictive technology model (PTM). http://ptm.asu.edu/,2012 (accessed Oct 7, 2015).
[8] S. Chatterjee, S. Salahuddin, S. Kumar, and S. Mukhopadhyay. Impact of self-heating on reliability of a spin-torque-transfer ram cell. IEEE Trans. on Electron Devices (TED), 59(3):791–799, March 2012.
[9] A. Chen. Feasibility Analysis of High-Density Spin-Transfer-Torque Random-Access-Memory With Shared Access Transistor Structure. IEEE Electron Device Letters (LED), 36(12):1325–1328, December 2014.
[10] A. Chen. Feasibility analysis of high-density sttram designs with crossbar or shared transistor structures. In Device Research Conference (DRC), pages 295–296, June 2014.
[11] X. Dong, C. Xu, and Y. Xie. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. http://nvsim.org/wiki/index.php?title=Download, 2012 (accessed June 20, 2015).
[12] X. Fong, S. H. Choday, P. Georgios, C. Augustine, and K. Roy. Purdue Nanoelectronics Research Laboratory Magnetic Tunnel Junction Model 1.0.0. https://nanohub.org/publications/16, 2014 (accessed Oct 7, 2015).
[13] X. Fong, Y. Kim, R. Venkatesan, S. H. Choday, A. Raghunathan, and K. Roy. Spintransfer torque memories: Devices, circuits, and systems. Proceedings of the IEEE (JPROC), 104(7):1449–1488, July 2016.
[14] A. Gebregiorgis, M. Ebrahimi, S. Kiamehr, F. Oboril, S. Hamdioui, and M. B. Tahoori. Aging mitigation in memory arrays using self-controlled bit-flipping technique. In The 20th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 231–236, January 2015.
[15] S. Ikeda, J. Hayakawa, Y. Ashizawa, Y. M. Lee, K. Miura, H. Hasegawa, M. Tsunoda, F. Matsukura, and H. Ohno. Tunnel magnetoresistance of 604% at 300K by suppression of Ta diffusion in CoFeB/MgO/CoFeB pseudo-spin-valves annealed at high temperature. Applied Physis Letter (AIP), 93(8), 2008.
[16] Y. Joo, D. Niu, X. Dong, G. Sun, N. Chang, and Y. Xie. Energy- and Endurance-Aware Design of Phase Change Memory Caches. In Design, Automation Test in Europe Conference Exhibition (DATE), pages 136–141, 2010.
[17] K. Joshi, S. Mukhopadhyay, N. Goel, and S. Mahapatra. A Consistent Physical Framework for N and P BTI in HKMG MOSFETS. In IEEE International Reliability Physics Symposium (IRPS), pages 5A.3.1–5A.3.10, 2012.
[18] H. Kaushal and P. Eswaran. Multi-sram reducing power through recovery-boosting. In International Conference on Devices, Circuits and Systems (ICDCS), pages 268–271, 2012.
[19] J. Kim, K. Ryu, S. H. Kang, and S.-O. Jung. A Novel Sensing Circuit for Deep Submicro Spin Transfer Torque MRAM (STT-MRAM). IEEE Trans. on VLSI (TVLSI), 20(1):181–186, 2012.
[20] T. T. Kim and Z. H. Kong. Impacts of NBTI/PBTI on SRAM Vmin and Design Techniques for SRAM Vmin Improvement. International SoC Design Conference (ISOCC), pages 163–166, 2011.
[21] S. V. Kumar, C. H. Kim, and S. S. Sapatnekar. Impact of NBTI on SRAM Read Stability and Design for Reliability. In International Symposium on Quality Electronic Design (ISQED), pages 6–11, 2006.
[22] Y. Kunitake, T. Sato, and H. Yasuura. Signal Probability Control for Relieving NBTI in SRAM Cells. In International Symposium on Quality Electronic Design (ISQED), pages 660–666, 2010.
[23] C.-K. Luk, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation. In ACM SIGPLAN conference on Programming language design and implementation (PLDI), pages 190–200, 2005.
[24] S. Mahapatra, N. Goel, S. Desai, S. Gupta, B. Jose, S. Mukhopadhyay, K. Joshi, A. Jain, A. E. Islam, and M. A. Alam. A Comparative Study of Different Physics-Based NBTI Models. IEEE Trans. on Electron Devices (TED), 60(3):901–916, 2013.
[25] H. Mahmood, M. L. M. Poncino, and E. Macii. Energy/Lifetime Cooptimization by Cache Partitioning with Graceful Performance Degradation. IEEE Trans. on VLSI (TVLSI), 22(8):1705–1715, August 2014.
[26] M. Meijer, J. P. de Gyvez, B. Kup, B. van Uden, P. Bastiaansen, M. Lammers, and M. Vertregt. A forward body bias generator for digital cmos circuits with supply voltage scaling. In IEEE International Symposium on Circuits and Systems (ISCAS), pages 2482–2485, May 2010.
[27] H. Mostafa, M. Anis, and M. Elmasry. Adaptive Body Bias for Reducing the Impacts of NBTI and Process Variations on 6T SRAM Cells. IEEE Trans. on CAS I: Regular Paper (TCSI), 58(12):2859–2871, 2011.
[28] A. Nigam, C. W. Smullen, V. Mohan, E. C. S. Gurumurthi, and M. Stan. Delivering on the Promise of Universal Memory for Spin-transfer Torque RAM (STT-RAM). In IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 121–126, 2011.
[29] H. Park, R. Dorrance, A. Amin, F. Ren, D. Markovic, and C. K. K. Yang. Analysis of sttram cell design with multiple mtjs per access. In IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pages 53–58, June 2011.
[30] S. S. P. Parkin, K. P. Roche, M. G. Samant, P. M. Rice, R. B. Beyers, R. E. Scheuerle, E. J. O’Sullivan, S. L. Brown, J. Bucchigano, D. W. A. amd Yu Lu, and M. Rooks. Exchange-biased Magnetic Tunnel Junctions and Application to Nonvolatile Magnetic Random Access Memory. Journal of Applied Physics (AIP), 85(8), 1999.
[31] B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy. Negative bias temperature instability: Estimation and design for improved reliability of nanoscale circuit. IEEE Trans. on CAD (TCAD), 26(4):743–751, April 2007.
[32] F. Ren, H. Park, R. Dorrance, Y. Toriyama, C. K. K. Yang, and D. Markovic. A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer rams (stt-rams). In International Symposium on Quality Electronic Design (ISQED), pages 275–282, March 2012.
[33] N. Rohbani, M. Ebrahimi, S. G. Miremadi, and M. B. Tahoori. Bias Temperature Instability Mitigation via Adaptive Cache Size Management. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), PP(99):1–11, 2016.
[34] J. Shin, V. Zyuban, P. Bose, and T. M. Pinkston. A proactive wearout recovery approach for exploiting microarchitectural redundancy to extend cache sram lifetime. In International Symposium on Computer Architecture (ISCA), pages 353–362, 2008.
[35] T. Siddiqua and S. Gurumurthi. Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 393–398, 2010.
[36] T. Siddiqua and S. Gurumurthi. Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 20(4):616–629, April 2012.
[37] R. Vattikonda, W. Wang, and Y. Cao. Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design. In ACM/IEEE Design Automation Conference (DAC), pages 1047–1052, 2006.
[38] B. Wicht. Current Sense Amplifiers for Embedded SRAM in High-Performance Systemon-a-Chip Designs. Springer-Verlag Berlin Heidelberg, New York, 2003.
[39] B. Wu, Y. Cheng, Y. Wang, A. Todri-Sanial, G. Sun, L. Torres, and W. Zhao. An architecture-level cache simulation framework supporting advanced pma stt-mram. In IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pages 7–12, July 2015.
[40] C. Xu, D. Niu, X. Zhu, S. H. Kang, M. Nowak, and Y. Xie. Device-architecture cooptimization of stt-ram based memory for low power embedded systems. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 463–470, 2011.
[41] C. Xu, Y. Zheng, D. Niu, X. Zhu, S. H. Kang, and Y. Xie. Impact of write pulse and process variation on 22nm finfet-based stt-ram design: A device-architecture cooptimization approach. IEEE Transactions on Multi-Scale Computing Systems (TMSCS), 1(4):195–206, October 2015.
[42] X. Yuan. Modeling, architecture, and applications for emerging memory technologies. IEEE Design and Test (MDT), 28(1):44–51, Jan. 2011.
[43] S. Zafar, Y. Kim, V. Narayanan, C. Cabral, V. Paruchuri, B. Doris, J. Stathis, A. Callegari, and M. Chudzik. A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates. IEEE Symp. VLSI Technol. Dig. Tech. Paper (VLSIT), pages 23–25, 2006.
[44] S. Zafar, A. Kumar, E. Gusev, and E. Cartier. Threshold voltage instabilities in high-κ gate dielectric stacks. IEEE Trans. in Device and Materials Reliability (IRPS), 5(1):45– 64, March 2005.
[45] W. Zhao, C. Chappert, V. Javerliac, and J. P. Noziere. High speed, high stability and low power sensing amplifier for mtj/cmos hybrid logic circuits. In IEEE Transactions on Magnetics (TMAG), pages 3784–3787, October 2009.
[46] P. Zhou, B. Zhao, J. Yang, and Y. Zhang. Energy reduction for stt-ram using early write termination. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 264–268, November 2009.