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研究生: 陳吉智
Chen, Chi-Chih
論文名稱: 不同閘極氧化層厚度之n型通道橫向擴散金氧半場效電晶體其特性之研究
The characteristics of n-channel lateral diffused metal-oxide-semiconductor (LDMOS) field effect transistors with different gate oxide thickness
指導教授: 陳志方
Chen, Jone Fang
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2004
畢業學年度: 92
語文別: 英文
論文頁數: 69
中文關鍵詞: 閘極氧化層電晶體橫向擴散
外文關鍵詞: ldmos, gate oxide
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  •   於此篇論文,我們利用一點零微米製程技術之n型通道橫向擴散金氧半場效電晶體針對不同閘極氧化層厚度做其特性之探討。
      文中針對不同閘極氧化層厚度之電晶體探討閘極氧化層厚度對於元件基本特性之影響。並於不同操作溫度下量測元件特性,以討論元件於高溫操作時之特性。最後針對不同閘極氧化層厚度之元件,以高於操作電壓之條件使其加速退化,用以討論不同閘極氧化層厚度之退化行為,並得出厚閘極氧化層之元件其最大退化隨閘極電壓之增加而增加;而薄閘極氧化層元件之最大退化則發生於最大基極電流之閘極電壓。

      In this thesis, the characteristics of Lateral Diffused Metal-Oxide-Semi- conductor (LDMOS) field effect transistors based on 1.0μm technology with different gate oxide thickness are investigated.
      The characteristics of LDMOS transistors with different gate oxide thicknesses are examined. The temperature dependence of device parameters is studied under elevated operating temperature. Constant voltage stress is performed on devices with different gate oxide thickness to see the impact of gate oxide thickness on parameter degradation. Different degradation behavior was found that the maximum degradation of thick gate oxide device increases with gate stress voltage. While in thin gate oxide device, the maximum degradation remains at peak substrate current condition.

    Abstract (Chinese) Ⅰ Abstract (English) Ⅱ Acknowledgements Ⅲ Contents Ⅳ Figure Captions Ⅵ List of Tables Ⅷ List of Symbols Ⅸ Chapter 1 Introduction 1 Chapter 2 Structure & Operation of LDMOS Transistor 2.1 Introduction 8 2.2 Structure of LDMOS Transistors 8 2.3 Operating Principle of LDMOS Transistor 9 2.4 Breakdown Mechanism 10 2.5 Implementation of LDMOS Transistor 12 2.6 Summary 15 Chapter 3 Measurements on LDMOS Transistors with Different Gate Oxide Thickness 3.1 Introduction 18 3.2 Measure Methodology 18 3.2.1 ID-VD Measurement 19 3.2.2 ID-VG Measurement 20 3.3 Measurement Results & Discussion 20 3.3.1 Measurements on Different Structure and Size (W/L) 21 3.3.2 Measurements under Different Temperature 23 3.3.3 Measurements on Devices with Different Gate Oxide Thickness 26 3.4 Summary 29 Chapter 4 Hot-Carrier Degradation in LDMOS Transistors with Different Gate Oxide Thickness 4.1 Hot-Carrier Effects in LDMOS Transistors 51 4.2 Device Degradation in Different Gate Oxide Thickness 53 4.3 Summary 54 Chapter 5 Conclusion 66 References 68

    [1]B. J. Baliga, “An overview of smart power technology,” IEEE Trans. Electron Devices, vol. 38, pp. 1568, July 1991.
    [2]Der-Gao Lin, S. Larry Tu, Yee-Chaung See, and Pak Tam, “A novel LDMOS structure with a step gate oxide,” IEEE IEDM, 10-13 pp. 963-966, Dec. 1995.
    [3]A. Moscatelli, A. Merlini, G. Croce, P. Galbiati, C. Contiero, “LDMOS implementation in a 0.35 μm BCD technology (BCD6),” ISPSD, pp. 323- 326, May 2000.
    [4]Pattanayak, D. Poksheva, J. Downing, R. Akers, L. “Fringing Field Effect in MOS Devices,” IEEE Trans. CHMT, vol. CHMT-5, pp. 127-131, Mar. 1982.
    [5]V. P. O’Neil and P. G. Alonas, “Relation Between Oxide Thickness and The Breakdown Voltage of a Planar Junction with Field Relief Electrode,” IEEE Trans. Electron Devices, vol. ED-26, pp. 1098-1100, 1979.
    [6]J. J. Liou, A. Ortiz-Conde and F. Garcia Sanchez, “Extraction of the Threshold Voltage of MOSFETs: an Overview,” IEEE IEDM, pp. 31-38, Aug. 1997.
    [7]S. M. Sze, Semiconductor Devices, Physics and Technology, 2nd ed. John Wiley & Sons, 2002.
    [8]J. R. Brews et al., “Subthreshold Behavior of Uniformly and Nonuniformly Doped Long-Channel MOSFET,” IEEE Trans. Electron Devices, ED-26 (9), pp. 1282, Sep. 1979.
    [9]L. D. Yau, “A simple theory to predict the threshold voltage of short-channel IGFETs,” Solid-State Electronics, 17, pp. 1059, 1974.
    [10]S. Wolf, Silicon Processing for the VLSI Era Volume 3: The Submicron MOSFET, Lattice Press, pp. 222, 1995.
    [11]A. Sabnis and J. Clemens, “Characterization of the electron mobility in the inverted <100> Si surface,” in IEDM Tech. Dig., pp. 18-21, 1979.
    [12]M. Pocha and R. Dutton, “Threshold voltage controllability in double-diffused MOS transistors,” IEEE Tran. Electron Devices, vol. ED-21, pp. 778-784, Dec. 1974.
    [13]R. S. Mueller and T. S. Kamins, Device Electronics for Integrated Circuits, 2nd ed. New York: Wiley, pp. 56, 1986.
    [14]G. Groesenken, J. P. Collinge, H. E. Maes, J. C. Alderman and S. Holt, “Temperature dependence of threshold voltage in thin-film SOI MOSFET’s,” IEEE Electron Device Lett., vol. 11, pp. 329-332, Aug. 1990.
    [15]F. S. Shoucair, “Scaling, subthreshold and leakage current matching characteristics in high-temperature (25-250) VLSI CMOS devices,” IEEE Trans. CHMT, vol. 12, Dec. 1989.
    [16]S. M. Sze, Physics of Semiconductor Devices, 2nd ed, pp. 105, John Wiley & Sons, 1981.
    [17]M. Pocha and R. Dutton. “Avalanche breakdown in high-voltage DMOS devices.” IEEE Trans. Electron Devices, vol. ED-23, pp. 1-4, Jan. 1976.
    [18]Y. S. Kim, J. G. Fossum, and R. K. Williams, “New physical insights and models for high-voltage LDMOST IC CAD,” IEEE Trans. Electron Devices, vol. ED-38, pp. 1641, 1991.

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