而隨著對於電子產品效能的需求，要如何在有限空間內放入更多電子元件則成了現今發展的重點。POP(Package on Package)技術就是一種發展出來的解決辦法，利用已經完成的封裝體(Package)在三維空間(高度)透過回焊將封裝體堆疊，形成三維系統封裝(3D system in Package SiP)，以達到更高密度封裝以及減少尺寸等目的。
本論文使用ANSYS 15.0以有限元素法針對POP型PSVFBGA封裝在96.5Sn3.5Ag錫球材料在改變構裝體外在風速下做精密熱傳模擬數值分析並且比較構裝體中各結構如晶片錫球之溫度變化與分佈圖。構裝體元件包含了基板(Substrate)、錫球(Solder Ball)、晶片(Chip)、封膠(Modling Compound)、散熱孔(Thermal Via)、印刷電路基板(Print Circuit Bpard PCB)。
熱傳分析部分，以Ellison熱對流理論之經驗公式，建立平板晶片熱傳分析模型，外在環境設定為50°C，並且改變晶片功率，在自然與強制對流改變不同風速的狀況下探討在POP構裝體中的溫度變化以及分佈圖。

This study uses finite element software ANSYS15.0 to analyze the heat transfer situation of Package-on-Package(POP) assembly. We observe the temperature distribution of the POP assembly, and change the power of the logic chip and memory chip to observe the influences.

[1]Moody Dreiza, Akito Yoshida, Jonathan Micksch, Lee Smith, "堆疊式封裝層疊(PoP)設計指南", 電子工程專輯, October 2005.

[2] K.W. Shim, and W.Y. Lo, “Solder Fatigue Modeling of Flip-Chip Bumps in Molded Packages”, IEEE International Electronic Manufacturing Technology, pp. 109-114, 2006.

[3] K. Biswas, S. Liu, X. Zhang, T.C. Chai, “Effects of detailed substrate modeling and solder layout design on the 1^st and 2^nd level solder joint reliability for the large die FCBGA”, IEEE International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, pp. 1-7, 2008.

[4] H.U. Akay, Y. Liu, M.Tassaian, “Simplification of Finite Element Models for Thermal Fatigue Life Prediction of PBGA Packages”, ASME Journal of Electronic Packaging, Vol.125, pp.347-353, 2003.

[5] J.H. Lau, X. Zhang, S.K.W. Seah, K. Vaidyanathan, T.C. Chai, “Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and their Flip-Chip Microbumps”, IEEE Electronic Components and Technology Conference, pp.1073-1081, 2008.

[6] M. Pei and J. Qu, “Constitutive Modeling of Lead-Free Solders” , IEEE Advanced Packaging Materials: Processes, Properties and Interfaces, pp.45-49, 2005.

[7]吳輔庭“The Analysis of the thermal chraracterization and fatigue of package-on-package(pop) assembly”國立成功大學，2012

[8]Wei Lin, Min Woo Lee, "PoP/CSP Warpage Evaluation and Viscoelastic Modeling", Electronic Components and Technology Conference, 2008.

[9]Xiang Qiu, Jun Wang, "Study on Heat Dissipation in Package On Package (POP) ", 11th International Conference on Electronic Packaging Technology & High Density Packaging, 2010.

[10]許介雄“PBGA構造體附加散熱器的熱傳分析The study of heat transfer of PBGA package with Thermal Enchancement”國立成功大學，2009

[11]黃致澄”Fatigue analyasis for thermally enchanced FC-PBGA Assembly using lead free 95.5Sn4.0Ag0.5Cu Solder”國立成功大學，2015

[12]Atila Mertol,Member“Thermal Performance Comparison of High Pin Count Cavity-Up Enhanced Plastic Ball Grid Array (EPBGA) Packages ” IEEE Transactions on Components, Packaging,and Manufacturing Technology-Part B, Vol. 19,No.2,pp.427-443,1996

[13]G. Z. Wang, Z. N. Cheng, K. Becker, J. Wilde, “Applying Anand Model toRepresent the Viscoplastic Deformation Behavior of Solder Alloys”, Journal of Electronic Packaging, Vol.123, pp.247-253, 1998.

[14]A. Schubert, R. Dudek, H. Walter, E. Jung, A. Gollhardt, B. Michel, and H. Reichl, ”Reliability Assessment of Flip-Chip Assemblies with Lead-free Solder Joints”, IEEE Electronic Component and Technology Conference, pp.1246-1255, 2002.

[15]R. Dudek, H. Walter, R. Doering, and B. Michel, “Thermal fatigue modelling for SnAgCu and SnPb solder joints”, IEEE Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, pp.557-564, 2004.

[16]Miaowen Chen, Leo Huang, George Pan, Nicholas Kao, Don Son Jiang, “Thermal Analyses of a Package-on-Package(POP) Structure for Tablet Application” , 2014 IEEE 16th Electronics Packaging Technology Conference(EPTC)

[17]Abhilash R. Menon, Saket Karajgikar, Dereje Agonafer, "Thermal Design Optimization of a Package On Package", 25th IEEE SEMI-THERM Symposium, 2009.

[18]李國龍 1, * 張高華 2 劉后鴻 3 潘文峰 3 "田口方法對薄形細間距球柵陣列封裝之最佳化設計"Journal of Technology, Vol. 28, No. 1, pp. 15-23 (2013)