現代生活上隨處可見影像處理的應用，而縮放技術在影像處理中更扮演了重要的角色。在影片或圖片傳輸的過程中，常常會經過不同的媒體裝置顯示，例如:將手機相片輸入到電腦。不同的顯示裝置其解析度也不盡相同，要配合這些系統上的差異，便需要用到影像縮放技術來實現。
　　本篇論文在邊緣保留摺積插補演算法(EPI)的研究基礎上，提出新的銳利度調整演算法來提升縮放後的影像品質。EPI演算法是透過數值分析的誤差理論，基於此誤差理論推導出了線性插補法及摺積插補法。但是這個演算法在某些倍率下並無法達到最佳的影像品質。因此我們透過調整公式，在不同的倍率下使用不同的銳利度參數，使我們提出的演算法在各個倍率下都能得到最好的結果。而在加入銳利度參數的過程中，修正後的插補演算法依然能以低複雜度的運算呈現。由於現在環保意識的抬頭以及智慧型裝置的大量用電，為了到達省電的目的，我們進一步分析電路架構，將核心模組加入clock gating設計，以減少不必要的運算耗電。
　　實驗結果證明，我們提出的演算法有效提升縮放後的影像品質，並且保有低計算複雜度的特性以利於VLSI的實作。根據Synopsys Design Compiler 與TSMC 0.13"μm" 標準原件庫合成的結果，此電路所需的邏輯閘數為12.1K，最高工作時脈可達300MHz，且功率消耗為3.77mW，相較於EPI，我們改良後的演算法降低了16%的功率消耗。

　　The technique of image scaling plays an important role in the digital image processing applications in recent years. The image data will be shown on different devices during the process of transmission, such as sending photograph from a phone to a computer. However, as different devices provide different screen and resolution, image scaling becomes indispensable for the coordinate between different devices.
　　In order to achieve higher quality of the image after scaling, an improved algorithm is proposed based on the research of Edge-Preserving Convolution Interpolation (EPI). The EPI algorithm derives linear and convolution interpolation according to error theory, yet it cannot obtain the higher image quality at some scaling magnifications. The equation is improved by using a controllable sharpness coefficient to obtain a higher result in every magnification. While applying the coefficient into the equation, this algorithm still retains the characteristic of low complexity. Due to the rise of environmental consciousness as well as large power consumption of smart devices, the circuit architecture is further analyzed and the Clock Gating technique is applied to the core module to reach the goal of low power.
　　Experimental results show that the algorithm can effectively enhance the quality of image scaling and is feasible for VLSI implementation with low complexity. By using Synopsys Design Compiler and TSMC 0.13"μm" cell library, the synthesis results show that the circuit can achieve 300MHz with gate counts of 12.1K and the total power consumption is 3.77mW. As comparing to the original EPI, the improved method reduces the power consumption by 10~16%.

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