本論文旨在研製一套以FPGA為基礎之語音辨識平台，基於硬體設計的需求提出改良式的辨識演算法，以提高運算的效率。隨著電腦的普及化，人機介面已逐漸發展成熟，除了ㄧ般的手控操作，更以達到人類與電腦間能直接藉由語言溝通為目標。由於語音處理技術的進步，許多提高語音辨識率的方法也不斷地被提出，故仍是一項發展中的技術。近年來由於SoC (System on Chip)的盛行，整合多功能的設計應用於各種數位產品，如：手機、PDA、數位相機等電子產品，已是目前的發展趨勢。若能結合語音處理的技術，將語音辨識應用於各種消費性電子產品中，透過使用者的語音輸入即可操作電子產品，取代傳統的手控方式，對使用者能提供不少的便利性，尤其是行動不便的使用者，更是一項福音。
此外，為了降低FPGA內部空間的浪費，本論文針對各項設計進行改良，以達到更有效率的FPGA容量應用。在程式編輯方面，是以硬體描述語言(Verilog)來實現語音辨識演算法，經由改良式動態時軸校正(dynamic time warping, DTW)演算法，實現硬體語音辨識工作。經軟體模擬與硬體測試後，驗證本論文所設計之語音辨識系統可以確實地進行辨識的工作，達到與軟體模擬時一樣的效果，其辨識率達九成，運算速度卻快了57倍左右。

As the popularization of the computer, human interface is developed gradually due to more and more requirements of the interaction between human and machine. One of the solutions is the speech process technology. Furthermore, based on the speech process technology, several methods are constantly proposed to raise recognition accuracy. Additionally, the design of various digital products which combined with multi-functional has applied by System on Chip (SoC) such as the cell-phone, PDA, digit camera, etc.
Inspired by the developments of speech process technology, a FPGA-based speech recognition system with improved DTW algorithm is proposed in this thesis. This system is verified by software simulation and hardware implementation. In practice, the speech recognition system designed in this thesis can execute speech recognition accurately and match the result with software simulation.

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