| 研究生: |
葉俊吾 Yeh, Junwu |
|---|---|
| 論文名稱: |
運用類神經網路建構SMT錫膏印刷製程品質管制系統 Using Artificial Neural Networks to Build a Quality Control System of SMT Stencil Printing Process |
| 指導教授: |
楊大和
Yang, Taho |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 製造工程研究所 Institute of Manufacturing Engineering |
| 論文出版年: | 2002 |
| 畢業學年度: | 90 |
| 語文別: | 中文 |
| 論文頁數: | 105 |
| 中文關鍵詞: | 錫膏印刷 、類神經網路 、表面黏著技術 、實驗設計 |
| 外文關鍵詞: | Neural Networks, Design of Experiment, Stencil Printing, SMT |
| 相關次數: | 點閱:105 下載:5 |
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為因應現今消費性電子產品的輕、薄、短、小趨勢,電子組裝技術亦隨著不斷改進。表面黏著組裝技術 (Surface Mount Technology, SMT) 已加速地取代傳統波焊製程 (Wave Soldering) ,儼然成為現代電子組裝產業主流,其製程優點在於降低生產成本並製造出高品質之電子產品。但於極端複雜的表面黏著組裝技術生產環境裡,製程中充滿著許多不確定的生產變數組合,尤其是在高密度之電子元件組裝,更成為基板組裝業之重大課題。若無法妥善控管製程參數及原物料特性,極可能產生不良焊性 (Solderability) ,導致產品品質下降、增加額外之生產成本;根據文獻及業界資深工程師的經驗得知,52%~71%之焊性不良源起於錫膏印刷製程 (Solder Paste Printing Process)。
本研究針對錫膏印刷製程單元,利用8個重要參數(錫膏黏度、鋼板厚度、零件腳距、鋼板與銲墊比例、間隙、印刷速度、刮刀壓力、錫膏顆粒)以分析錫膏印刷製程。並運用實驗設計及類神經網路以建構一套製程品質管制之衡量標準,並可配合統計製程品管(SPC)軟體以提昇焊性及產品品質。
Surface Mount Technology (SMT) assembly is the placement and attachment of electronic components to the surface of a printed circuit board, and it has become the key technology to transform manufacturing in the electronics industry to continuously respond to the needs of the global market. The relationship between the input/output variables in SMT acts nonlinearly and severely. The stencil printing is one of the most critical stages and accounts for 52~71% of overall soldering defects.
This research will help in understanding the solder paste stencil printing process and identifying the critical variables that influence the volume of deposited solder paste. Through design of experiment and neural networks, a quality control system of stencil printing is established that helps engineers in troubleshooting the malfunctioned process and to improve solderability.
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