傳統半導體製程中，電晶體微縮已逐漸逼近物理極限，使得繼續縮小電晶體變得越來越困難且昂貴。現代封裝的重點已從過去單純的「更小、更快」，轉變為追求多功能性、高附加價值與異質整合（Heterogeneous Integration），於是先進封裝的需求因應而生，這促使先進封裝技術的興起，這些技術旨在透過異質整合而非單片縮放來維持效能成長。在這些創新中，面板級封裝（PLP）脫穎而出，成為一種極具變革性的架構，它透過從傳統的 300 毫米圓形晶圓轉向大型矩形面板，實現了更高的生產效率和顯著的成本優勢，在相同邊長特徵尺寸的情況下，矩形面板顯然能夠更好利用空間塞入比圓形晶圓更多的晶片，產生更大的經濟效益。
然而 PNL結構在大面積與多材料（如RDL、PI、CPD等）的堆疊下，在經過溫度變化後，各材料熱膨脹係數（Coefficient of Thermal Expansion, CTE）不一致，導致結構產生翹曲（Warpage），影響後續製程，可能導致功能失效或可靠度下降。為了能夠控制翹曲的影響，本研究主要透過有限元素分析軟體Ansys來進行翹曲分析，並驗證模擬結果是否能與實際量測的結果有相同趨勢，並紀錄各製程站點的參考溫度，以用於未來能夠以此參考溫度，來預測最佳化結構或是替換其他材料的可能行為趨勢。
本研究透過將Python 與 Ansys 做結合，開發了介面化參數化自動建模、自動化前處理，以及後續的自動化分析，結果顯示，開發之自動化系統能有效提升模擬效率與精度。在技術性能上，透過共享節點技術使前處理時間縮短 90%，記憶體用量從 15GB 降至 1GB，並達成 83.8% 的運算加速。在模擬驗證方面，除了獨立校正能面板級封裝在前四個站點（Station A~D）中，模擬與實驗的誤差均精準控制在 10% 以內，其中最低誤差僅 0.84%，後續採用的延續校正策略能精準捕捉製程中的翹曲反轉，使最終站點誤差收斂至 8.25%。此外，該流程亦成功應用於 HFCBGA 封裝，證明其具備從宏觀面板到微觀封裝的泛用性與取代人工調校的潛力。

In traditional semiconductor manufacturing processes, transistor scaling is gradually approaching its physical limits, making further miniaturization increasingly difficult and expensive. The focus of modern packaging has shifted from simply being "smaller and faster" to pursuing multi-functionality, high added value, and Heterogeneous Integration. Consequently, the demand for advanced packaging has emerged, driving the rise of technologies designed to sustain performance growth through heterogeneous integration rather than monolithic scaling. Among these innovations, Panel-Level Packaging (PLP) stands out as a highly transformative architecture. By transitioning from traditional 300 mm round wafers to large rectangular panels, it achieves higher production efficiency and significant cost advantages. Under the same characteristic edge length, rectangular panels can obviously utilize space more effectively to accommodate more chips than round wafers, generating greater economic benefits.
However, in the PNL structure, the large-area stacking of multiple materials (such as RDL, PI, CPD, etc.) leads to mismatched Coefficients of Thermal Expansion (CTE) during temperature variations. This CTE mismatch induces structural warpage, which affects subsequent manufacturing processes and may result in functional failure or degraded reliability. To control the impact of warpage, this study primarily employs the finite iv element analysis software Ansys to conduct warpage simulations and verifies hether the simulation results align with the trends of actual empirical easurements. Furthermore, the reference temperatures at various process stations are recordedso that they can be utilized in the future to predict the potential ehavioral trends for structural optimization or material substitution.
By integrating Python with Ansys, this study developed GUI-based parametric automated modeling, automated pre-processing, and subsequent automated analysis. The results indicate that the developed automated system effectively enhances simulation fficiency and precision. In terms of technical performance, the implementation of hared Topology technology reduced pre-processing time by 90%, decreased memory usage from 15GB to 1GB, and achieved an 83.8% acceleration in computational speed. Regarding simulation verification, under the independent calibration strategy for panel-level packaging, the simulation errors for the first four stations (Stations A to D) were precisely controlled within 10%, with the lowest error being merely 0.84%. The subsequently employed sequential calibration strategy accurately captured the warpage reversal during the process, successfully converging the error at the final station to 8.25%. Furthermore, this workflow was successfully applied to the HFCBGA package, demonstrating its versatility spanning from macroscopic panels to microscopic packages, as well as its robust potential to replace manual fine-tuning.

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