本論文利用TSMC提供之0.18 μm CMOS製程與IE3D模擬軟體，實現使用螺旋共振器來合成60-GHz帶通濾波器，共振器採取螺旋形狀主要為可減少共振器所需要的面積，大幅縮小濾波器的面積，並提高選擇性。首先設計之螺旋共振器採同平面耦合，饋入以寬邊耦合方式，增加螺旋共振器之間耦合量，在兩共振器耦合處下方，挖掉部分地，以減少感應磁場在接地面引起的損耗。其次設計之帶通濾波器採取上下耦合方法來增加耦合量，避免因缺陷地而影響共振器的共振頻率。亦縮小pad的大小以減少饋入線與pad間的不連續面效應，濾波器的面積約縮小72.1 %。 量測與模擬不符合之處，經過使用不同模擬軟體模擬比較，發現使用HFSS模擬軟體模擬相同結構與環境參數，可得到與量測值相當吻合的結果。

This thesis presents the design and implementation of the 60-GHz CMOS bandpass filters using spiral-resonators. The filters are fabricated with TSMC 0.18-µm standard CMOS process. IE3D EM solver is used for design simulation. The spiral resonators can reduce the filter and improve the selectivity. Two CMOS filters have been designed. The first design uses edge-coupled resonators and the broadside-coupled feed line. The defected ground has been used to enhance the coupling between the resonators. The second design adopts the broadside-coupled resonators without a defected ground. It also reduces the pad size to decrease the discontinuities between the feed line and the pads and achieve a size reduction of 72 %. The discrepancy between simulation and measurement has been checked by a 3-D EM solver, Ansoft HFSS, for debugging.

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