在現代電路設計流程中，工程變更命令（ECO）逐漸成為一個重要的技術專門用來解決後期發現設計不足之處。這些設計缺陷，包括功能錯誤和時序違反的行為，工程變更單更命令通常藉由多餘元件(Spare Cell)來達到除錯的效果。傳統上，功能錯誤和時序違反都有各自的工程變更命令來分開處理。因此，他們無法適當地分配多餘元件和造成不必要的多次變更來實現設計完善。在本文中，我們提出了一個方法，可同時執行功能錯誤和時序違反的修正。基於整數線性規劃（ILP）過程中，我們可以將多餘元件做最有效的分配以達到功能錯誤和優化時序的目的。此外，我們還提出了一個能有效加速整數線性規劃的方法，以進一步提減少執行時間。根據五個工業實例的實驗結果可展示出我們有效力和效率的方法。

In modern IC design, Engineering Change Order (ECO) has become an important technique for resolving late-detected design de ciencies. These design de ciencies, including functional errors and timing violations, are usually corrected by ECO using spare cells. Traditionally, functional errors and timing violations are solved by functional ECO and timing ECO, separately. Therefore, they would not assign spare cells appropriately and cause unnec- essary iterations to achieve design convergence. In this paper, we propose a framework to perform functional and timing ECO simultaneously. Based on an integer linear programming (ILP) formulation, we can remove all functional errors and optimize timing-violated paths with an effective assignment of spare cells. Moreover, a reduction method to further reduce execution time is presented. Experimental results based on five industrial benchmarks are given to demonstrate the effectiveness and effciency of our approach.

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