射頻IC電感之設計與模擬
郭鴻毅 ＊ 王水進 ＊＊
國立成功大學微電子工程研究所
摘 要
在高頻類比積體電路設計中，晶片式電感元件大都是以GaAs或是BiCMOS的製程為主，其主要原因乃是因為這兩種製程所使用之基板（substrate）具有低摻雜濃度(亦即高阻值)的特徵，可使元件的整體表現較接近本質元件（intrinsic devices）的特性，減少了許多的寄生效應（parasitic-effects），提供較高的截止頻率（cut-off frequency），然而其製程成本與難度目前矽半導體VLSI製程之數倍。目前矽半導體VLSI-CMOS製程所使用之基板係以高掺雜、低阻值者居多，此種基板可在電路操作在低頻時，防止CMOS電路栓鎖的發生。但是操作在高頻時，低阻質的基板卻很容易損耗電路的功率而無法達到高品質因素（quality factor）的要求，此對以矽半導體為基礎、整合射頻被動元件與射頻積體電路而言，乃是一難解的問題。
本篇論文係針對應用多晶矽遮蔽技術於繞線式晶片電感(solenoid IC inductor)的設計與模擬進行探討。藉由傳統螺旋式電感的基本理論模型延伸到繞線式電感進行設計，找出各項設計重參數找出最佳化的設計，接著探討多晶矽基礎理論應用於繞現式電感之可行性，進行模擬並找出對應的設計守則。
作者* 指導教授**

Design and Simulation of RFIC Inductor
Hon-yi Kuo * Shui-Jinn Wang **

Institute of Microelectronics &
Department of Electrical Engineering
National Cheng Kung University
Tainan, Taiwan, R.O.C.
Thesis for Master of Science,
June. 2003

Abstract
This paper presents an on-chip solenoid inductor with novel patterned poly-shielding. The whole process could be realized in standard silicon technology without additional processing steps. This lead to a higher inductance and better quality factor with smaller chip area. Simulation results show this novel design increase the quality factor up to 30% and reduce the loss due to the substrate. We will realized this design with TSMC 035 process in the further future and make the measurement to fix the model.
Author* Advisor**

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