由於CMOS製程的進步，電晶體的尺寸持續的縮小，因此效能得到改善。同時，隨著電晶體尺寸的減小，功率密度和溫度持續的上升，可靠度已經變成主要的設計考量。動態電壓與頻率調整(DVFS)是一個廣泛被用來減少多核心系統動態功率之技術，並且可以被用來改善溫度和系統可靠度。以全晶片(chip-based)為單位之動態電壓與頻率調整方式最早被提出，然而，因為較低的彈性而效果較差。因此，以單核心(core-based)為單位之動態電壓與頻率調整方法被提出，此方法可達到很好的彈性與較佳的改善結果。但是，由於每個核心皆需一個電壓穩壓器，這個技術需要較高的硬體與設計成本。所以，以單群集(cluster-based)為單位之動態電壓與頻率調整方法在近年中被提出，作為在全晶片與單核心動態電壓與頻率調整中的折衷方法。然而，此技術是在編譯時決定群集分佈，無法在執行時動態調整，而且只有以減少功率消耗為目標。
在本篇論文中，我們提出在執行時以單群集為單位之動態電壓與頻率調整技術，以改善系統溫度和可靠度為目標。這篇論文考慮溫度和受到負偏壓溫度不穩定性(NBTI)影響下的故障前平均時間(MTTF)，並且提出演算法根據核心的狀態在執行時週期性的重新決定每一群集的核心分佈，並提出一個溫度與可靠度感知之動態電壓與頻率調整方法來達到更好的改善。
和以單核心為單位之動態電壓與頻率調整方法相比，我們提出的技術可在只增加6%的能量與延遲時間積(EDP)下，降低12.75℃的最高溫度，8.99℃的平均溫度，減少67.96%的熱點數量，以及改善20.34% 在NBTI影響下的MTTF。和非對稱群集(asymmetric cluster)之動態電壓與頻率調整方法相比，我們提出的技術可以減少3%的能量消耗，改善2%的能量與延遲時間積(EDP)，降低14.56℃的最高溫度及9.46℃的平均溫度，減少69.21%的熱點數量，以及改善27.61% 在NBTI影響下的MTTF。

As the advance of CMOS technology, transistor geometry keeps shrinking and transistor switching speed improves. Meanwhile, with reduced transistor geometry and increased power density and temperature, reliability has become a major concern. Dynamic voltage and frequency scaling (DVFS) is a widely used technique to reduce dynamic power consumption in multicore systems, and can be used to improve temperature and system reliability. The chip-based DVFS technique that the voltage and frequency of all cores are the same is first proposed; however, it is less effective due to less flexibility. The core-based DVFS technique that each core can have different voltage and frequency is proposed to achieve greater flexibility and better improvement. However, since each core requires its own voltage regulator, this technique will require significant hardware and design cost. The cluster-based DVFS technique is recently proposed, where several cores are grouped into a cluster and all the cores in the same cluster have the same voltage and frequency. However, this technique is done at compile time and is only targeted to reduce power consumption.
In this thesis, we propose an online cluster-based DVFS technique, targeting system temperature and reliability improvement. This technique considers the temperature profile and mean time to failure (MTTF) under the influence of the Negative Bias Temperature Instability (NBTI) effect, and proposes novel algorithms that periodically recluster cores according to the core states at runtime with cluster-based DVFS control for reliable multicore system design.
Compared to core-based DVFS, our proposed technique can achieve 12.75℃ reduction in maximum temperature, 8.99 ℃ reduction in average temperature, 67.96% reduction in the hotspot numbers, and 20.34% improvement in MTTF under the influence of the NBTI effect with 6% increase in EDP.
Compared to asymmetric cluster DVFS, our technique can achieve 3% reduction in energy, 2% reduction in EDP, 14.56℃ reduction in maximum temperature, 9.46℃ reduction in average temperature, 69.21% reduction in hotspot numbers, and 27.61% reduction in MTTF.

[1] S. Bandyopadhyay, Y. K. Ramadass, and A. P. Chandrakasan, “20uA to 100mA DC-DC converter with 2.8 to 4.2V battery supply for portable applications in 45nm CMOS,” in Proceedings of Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011, pp. 386-388.
[2] M. Basoglu, M. Orshansky, and M. Erez, “NBTI-aware DVFS:A New Approach to Saving Energy and Increasing Processor Lifetime,” in Proceedings of International Symposium on Low-Power Electronics and Design (ISLPED), 2010, pp. 253-258.
[3] C. Bienia, S. Kumar, J. P. Singh, and K. Li. “The PARSEC benchmark suite: Characterization and architectural implications,” in Proceedings of International conference on Parallel Architectures and Compilation Techniques (PACT), 2008, pp. 72-81.
[4] N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell,M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood, “The GEM5 Simulator,” in Computer Architecture News (CAN), 2011, pp. 1-7.
[5] X Chen, Z. Xu, H. Kim, P.V. Gratz, J. Hu, M. Kishinevsky, U. Ogras, and R. Ayoub, “Dynamic voltage and frequency scaling for shared resources in multicore processor designs,” in Proceedings of Design Automation Conference (DAC), 2013, pp. 114.
[6] R. Cochran, and S. Reda, “Consistent runtime thermal prediction and control through workload phase detection,” in Proceedings of Design Automation Conference (DAC), 2010, pp.62-67.
[7] S. Dighe, S. Vangal, P. Aseron, S. Kumar, T. Jacob, K. Bowman, J. Howard, J. Tschanz, V. Erraguntla, N. Borkar, et al. “Within-die Variation-Aware Dynamic-Voltage-Frequency Scaling Core Mapping and Thread Hopping for an 80-core Processor, ” in Proceedings of Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010, pp. 174-175.
[8] J.A. Hartigan and M.A. Wong, “Algorithm AS136: A k-means Clustering Algorithm,” Journal of the Royal Statistical Society Series, B,1979, pp. 100-108.
[9] S. Herbert and D. Marculescu, “Analysis of dynamic voltage/frequency scaling in chip-multiprocessors,” in Proceedings of International Symposium on Low-Power Electronics and Design (ISLPED), 2007, pp. 38–43.
[10] W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron and M.R. Stan, “HotSpot: a compact thermal modeling method for CMOS VLSI systems,” IEEE Transations on Very Large Scale Integration (VLSI) Systems, 2006, pp. 501-513.
[11] C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi. “An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget,” in Proceedings of International Symposium on Microarchitecture (MICRO), 2006, pp. 347-358.
[12] W. Kim, D. M. Brooks, and G. Wei, “A Fully-Integrated 3-Level DC/DC Converter for Nanosecond-Scale DVS with Fast Shunt Regulation,” in Proceedings of Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011, pp. 206-219.
[13] W. Kim, M. S. Gupta, G.-Y. Wei, and D. Brooks,“System level analysis of fast, per-core DVFS using on-chip switching regulators,” in Proceedings of International Symposium on High Performance Computer Architecture (HPCA), 2008, pp. 123–134.
[14] T. Kolpe, A. Zhai, and S. Sapatnekar, “Enabling improved power management in multicore processors through clustered DVFS,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, pp. 1 –6.
[15] S. Kudva and R. Harjani, “Fully-integrated on-chip DC-DC converter with a 450X output range,” IEEE Journal of Solid-State Circuits (JSSC), 2011, pp. 1940-1951.
[16] W. Lee, Y. Wang, and M. Pedram, “VRCon: Dynamic Reconfiguration of Voltage Regulators in a Multicore Platform,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, pp. 1-6.
[17] W. Lee, Y. Wang, and D. Shin , “Optimizing power delivery network in a smartphone platform,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2014, pp. 36-49.
[18] S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, “McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures,” in Proceedings of International Symposium on Microarchitecture (MICRO), 2009, pp. 469-480.
[19] Z. Liu, T. Xu, S. Tan, and Hai Wang, “Dynamic thermal management for multi-core microprocessors considering transient thermal effects,” in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 2012, pp. 473-478.
[20] J. Murray, R. Hegde, T. Lu, P. P. Pande, and B. Shirazi, “Sustainable dual-level DVFS-enabled NoC with on-chip wireless links,” in Proceedings of International Symposium on Quality Electronic Design (ISQED), 2013, pp. 135-142.
[21] J. Park, D. Shin, M. Pedram, and N. Chang, “Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern highperformance microprocessors,” in Proceedings of International Symposium on Low-Power Electronics and Design (ISLPED), Aug. 2010, pp. 419–424.
[22] B.C. Paul, K. Kang, H. Kuflouglu, M. A. Alam and K. Roy, “Impact of NBTI on the Temporal Performance Degradation of Digital Circuits,” IEEE Electron Device Letters, 2005, pp. 560-562.
[23] B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, “Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2007, pp. 743–751.
[24] N. Pinckney, K. Sewell, R. G. Dreslinski, D. Fick, T. Mudge, D. Sylvester, and D. Blaauw, “Assessing the Performance Limits of Parallelized Near-Threshold Computing,” in Proceedings of Design Automation Conference (DAC), 2012, pp. 1147-1152.
[25] H. Shen, J. Lu and Q. Qiu, “Learning based DVFS for simultaneous temperature, performance and energy management,” in Proceedings of International Symposium on Quality Electronic Design (ISQED), 2012, pp. 747-754.
[26] K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan,“Temperature-aware microarchitecture,” in Proceedings of International Symposium on Computer Architecture (ISCA), pp. 2–13, 2003.
[27] J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, “The Case for Lifetime Reliability-Aware Microprocessors,” in Proceedings of International Symposium on Computer Architecture (ISCA), 2004, pp. 276-287.
[28] H. Tajik, H. Homayoun, and N. Dutt, “VAWOM: Temperature and Process Variation Aware WearOut Management in 3D Multicore Architecture,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, pp. 1-8.
[29] Z. Toprak-Deniz, M. Sperling, J. Bulzacchelli, G. Still, R. Kruse, S. Kim, D. Boerstler, T. Gloekler, R. Robertazzi, K. Stawiasz, T. Diemoz, G. English, D. Hui, P. Muench, J. Friedrich, “Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor,” in Proceedings of Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, pp. 98-99.
[30] R. Vattikonda, W. Wang, and Y. Cao, “Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design,” in Proceedings of Design Automation Conference (DAC), 2006, pp. 1047–1052.
[31] M. Weiser, B. Welch, A. Demers, and S. Shenker, “Scheduling for Reduced CPU Energy,” in Proceedings of Symposium on Operating Systems Design and Implementation (OSID), 1994, pp. 13-23.
[32] M. Wens and M. Steyaert, “An 800mW Fully-Integrated 130nm CMOS DC-DC Step-Down Multi-Phase Converter, With On-Chip Spiral Inductors and Capacitors,” in Proceedings of Energy Conversion Congress and Exposition (ECCE), 2009, pp. 3706-3709.
[33] A.Y. Yamamoto, C. Ababei, “Unified system level reliability evaluation methodology for multiprocessor systems-on-chip,” in Proceedings of Green Computing Conference (IGCC), 2012, pp. 1-6.
[34] S. Zafar, B. Lee, J. Stathis, A. Callegar, and T. Ning, “A model for negative bias temperature instability (NBTI) in oxide and high k pFETs,” in Proceedings of International Symposium on VLSI Technology, pp. 208-209, 2004.