| 研究生: |
顏鴻銘 Ming, Hung |
|---|---|
| 論文名稱: |
適用小型飛機運輸系統需求雙匯流排架構下之航電可靠度性能驗證 Verification of Avionics Reliability Performance using Dual Data Bus System Infrastructure for Small Aircraft Transportation System |
| 指導教授: |
林清一
Lin, Chin E. |
| 學位類別: |
博士 Doctor |
| 系所名稱: |
工學院 - 航空太空工程學系 Department of Aeronautics & Astronautics |
| 論文出版年: | 2009 |
| 畢業學年度: | 97 |
| 語文別: | 英文 |
| 論文頁數: | 137 |
| 中文關鍵詞: | 雙匯流排 、可靠度 |
| 外文關鍵詞: | Dual Data Bus, Reliability |
| 相關次數: | 點閱:84 下載:2 |
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近數十年來,數位航電匯流排新技術之研發,已經成為航電系統重要且必要的角色,並藉以提升通用航空飛機的性能。整個系統網路的建構設計必須在可靠度與穩定性上接受更嚴格的驗證,而控制區域網路(CAN)在釵h應用上皆有極佳的性能。本論文探討研究在可靠度的考量下,將備援的觀念與技術植入以控制區域網路為基礎的航電系統中,並將時間觸發協定加入雙匯流排的架構中用以提升可靠度與穩定性。論文中採用不同的測試條件與模擬來驗證系統設計的性能。具有時間觸發協定與控制區域網路的硬體與軟體設計不僅能符合航電上的要求,並將成為一個可被接受的航電匯流排標準。
本論文建構與設計並驗證一個適合小型飛機數位航電的雙控制區域網路匯流排系統,這是強化標準單匯流排系統的延伸發展,其中並探討事件觸發與時間觸發的混合訊號影響程度,藉以改善系統的性能。為了達到雙航電匯流排目的,本論文採用不同的電路設計,雙通道記憶體映對方法與硬體電路選擇器的設計。雙通道記憶體映對方法具有比較高的可靠度,而硬體電路選擇器設計法在中央處理器(CPU)的負擔上比較小。
電路板的驗證測試延伸到與電腦結合控制的性能分析,在測試過程中並設計了一個結合主要飛行顯示器與資料傳輸交換介面的監控畫面軟體。每個節點在應用上都可以接到真正的儀器或感測器或者模擬訊號源。雙匯流排IP 板的設計除了性能上的驗證,本論文利用RELEX軟體與電路模組法則研究,本系統在可靠度與穩定性的分析探討中都得到相當的強化。
In recent decades, new technology developments on digital avionics data bus system have become important and necessary infrastructure to enhance future general aviation aircraft system. The reliability and stability of the adopted technology to affect the overall avionics system should be examined under system configuration design. Controller Area Network (CAN)-based data bus technology has presented its function capability for such applications. This dissertation surveys the reliability concerns on a redundancy design and performance of CAN-based avionics system. The time triggered protocol (TTP) is added onto the dual bus configuration to improve the system reliability and stability. System design and simulation on different scenarios are tested to verify the system performance. TTP-CAN hardware and software may become an acceptable data bus system design standard to meet aviation requirements.
This dissertation presents a prototype fabrication and verification on a dual CAN bus system for digital avionics for small aircraft systems, extending from a preliminary single CAN-bus architecture. For the proposed dual bus avionics, new IP board circuit designs are discussed using the memory mapping method and hardware selector method. And the control firmware are also conferred within the two methods, the systme CPU load using hardware selector is much less than the memory mapping.
The integrated circuit board has been fabricated for tests and extended into PC controlled operation. In the tests, a primary flight display suitable for small aircraft transportation system application is constructed with several functions for terminal data exchange control. Each node will be connected to real instruments or sensors, as well as several simulated signals. The proposed dual data bus integrates CAN plus TTP to enhance system performance in reliability and stability.
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