簡易檢索 / 詳目顯示

回結果列表
研究生： 陳藜方
Chen, Li-Fang
論文名稱： 十二位元每秒取樣兩千五百萬次之使用開迴路殘值放大器的管線式逐漸趨近式類比數位轉換器
A 12-bit 25-MS/s Pipelined-SAR ADC Using Open-Loop Residue Amplifier
指導教授： 王永和
Wang, Yeong-Her
吳伯昌
Wu, Po-Chang
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年： 2022
畢業學年度： 110
語文別： 英文
論文頁數： 90
中文關鍵詞： 開迴路殘值放大器 、動態邏輯電路 、管線式逐漸趨近式類比數位轉換器
外文關鍵詞： Open-loop Residue Amplifier, Dynamic Logic Circuit, Pipelined-SAR ADC
相關次數： 點閱：99  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 隨著晶片製程技術的發展帶動電晶體尺寸的微縮，如今晶片的性能與運作速度得以飛躍式提升。對於類比數位轉換器電路來說，製程技術的精進也幫助類比數位轉換器更容易達到高解析度、高速與低功耗的目標。其中逐漸趨近式類比數位轉換器是最值得被探討的。由於該架構內部電路中的數位電路占比高，而電晶體微縮時數位電路的功率消耗會大幅降低，因此相比其他類比數位轉換器其功率消耗最低。然而當應用於超高解析度時，由於內部架構中的電容數量會隨解析度提升而呈指數性增加，因此安定時間也隨之拉高，連帶降低其轉換效率。傳統管線式類比數位轉換器架構具備高速及高解析度的優點，但缺點是由於內部電路包含大量運算放大器，在運作時經常伴隨高功率損耗。因此，本論文結合傳統管線式與逐漸趨近式類比數位轉換器的技術，實現一個十二位元混和型管線式逐漸趨近式類比數位轉換器。
    為了縮短安定時間，本作品內部電路中的殘值放大器使用開迴路運算放大器。由於開迴路運算放大器會有增益誤差的問題，因此在逐漸趨近類比數位轉換器內的電容陣列採用可由參考電壓控制轉換器輸入區間的架構。而為了達到更高速的應用，因此在逐漸趨近類比數位轉換器內的控制邏輯電路採用動態邏輯電路架構，具體方式是透過時脈預充放電來達到時序傳遞與儲存的功能，藉此取代傳統D型正反器。本設計使用台積電 90-nm CMOS製程來實作晶片，晶片面積為700 × 700-μm2，操作電壓為1.2伏特及每秒達到兩千五百萬次取樣速度。

    Considering the rapid development of the chip process technology, the actual size of transistors has been drastically reduced. For analog-to-digital converter (ADC) circuits, advances in process technology also helps analog-to-digital converters to achieve high-resolution, high-speed and low-power consumption goals more easily. Among them, the successive-approximation register (SAR) ADC is considerably more worth of being discussed. Due to the high proportion of digital circuits in the internal circuits of this architecture, the power efficiency of the SAR ADC is always better than other analog digital converters. When ultra-high resolution is being applied, the gradual number of capacitors will automatically increase exponentially, according to which the conversion efficiency of the SAR ADC will reduce apparently. On the other hand, the traditional pipeline ADC has the unique advantages of high speed and high resolution. However, due to the large number of operational amplifiers included in the internal circuit, it has often been accompanied by high power loss during operation. Therefore, such kind of thesis combines the technologies which are in-detailly mentioned as above to realize a 12-bit hybrid pipelined-SAR ADC. In order to shorten the settling time, an open-loop residue amplifier has been used in this work. Since open-loop residue amplifiers suffer from gain errors, the capacitor array in the SAR ADC has been basically designed to utilize the actual reference voltage to completely control the converter’s input range. To achieve the intense high speed, a dynamic logic circuit structure was used as the control logic circuit in the SAR ADC. The identical specific method is to achieve the function of timing transfer and storage through clock pre-charge and discharge, thereby replacing the traditional D flip-flop.
    This work was fabricated in TSMC standard 90-nm CMOS process with a core area of 700 × 700-μm2, under 1.2-V operating voltage where the sampling rate is 25-MS/s.

    中文摘要 I Abstract III 致 謝 V CONTENTS VII FIGURE CAPTIONS X TABLE CAPTIONS XV Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization 4 Chapter 2 Fundamental of Analog-to-Digital Converter (ADC) 5 2.1 ADC Dynamic Parameters 5 2.1.1 Signal-to-Noise Ratio (SNR) 6 2.1.2 Signal-to-Noise and Distortion Ratio (SNDR) 8 2.1.3 Effective Number of Bits (ENOB) 9 2.1.4 Spurious Free Dynamic Range (SFDR) 10 2.1.5 Total Harmonic Distortion (THD) 11 2.1.6 Effect Resolution Bandwidth (ERBW) 12 2.2 ADC Static Parameters 13 2.2.1 Differential Nonlinearity (DNL) 14 2.2.2 Integral Nonlinearity (INL) 15 2.2.3 Offset Error 18 2.2.4 Gain Error 19 2.3 ADC Topologies and Architectures 20 2.3.1 Flash ADC 20 2.3.2 Sigma-Delta ADC 21 2.3.3 Pipelined ADC 24 2.3.4 Successive-Approximation Register (SAR) ADC 26 2.4 Hybrid ADC Architectures 29 Chapter 3 Pipelined SAR ADC Design Implementation 32 3.1 Pipelined SAR ADC Architecture 32 3.2 Stage 1st and 2nd SAR ADC 34 3.2.1 Bootstrapped Switch 34 3.2.2 Dynamic Comparator 37 3.2.3 Switched-Capacitor Array 40 3.2.4 SAR Control Logic 43 3.3 Residue Amplifier 46 3.3.1 Open-loop Operation Amplifier (OPAMP) 46 3.3.2 Common Mode Feedback (CMFB) 47 3.3.3 Bias Circuit 48 3.4 Digital Error Correction (DEC) 50 3.5 Layout Consideration 53 Chapter 4 Simulation and Measurement Results 55 4.1 Simulation Results 55 4.1.1 Bootstrapped Switch Frequency Analysis 55 4.1.2 Stage 1st SAR ADC Frequency Analysis 57 4.1.3 Stage 2nd SAR ADC Frequency Analysis 62 4.1.4 Operation Amplifier Simulation Analysis 67 4.1.5 Pipelined SAR ADC Circuit Integration Analysis 68 4.2 Chip Area and Micrograph 72 4.3 Experiment Environment 74 4.4 Measurement Results 77 4.5 Analysis of Measurement Problem 78 Chapter 5 Conclusions and Future Work 83 References 85

    [1] Harpe, Pieter & Makinwa, Kofi & Baschirotto, Andrea. (2018). Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design: Advances in Analog Circuit Design 2017. 10.1007/978-3-319-61285-0.
    [2] Y. Wu, J. Lan, M. Chen, F. Ye and J. Ren, "A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems," 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2020, pp. 3-6, doi: 10.1109/APCCAS50809.2020.9301652.
    [3] J. Li, X. Guo, J. Luan, D. Wu, L. Zhou, N. Wu, Y. Huang, H. Jia, X. Zheng, J. Wu, and X. Liu. 2020. "A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology" Electronics 9, no. 2: 375. https://doi.org/10.3390/electronics9020375
    [4] H. Huang, H. Xu, B. Elies and Y. Chiu, "A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation," IEEE Journal of Solid-State Circuits, vol. 52, no. 12, pp. 3235-3247, Dec. 2017, doi: 10.1109/JSSC.2017.2732731.
    [5] K. Uyttenhove and M. S. J. Steyaert, "Speed-power-accuracy tradeoff in high-speed CMOS ADCs," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 4, pp. 280-287, April 2002, doi: 10.1109/TCSII.2002.801191.
    [6] B. P. Brandt and B. A. Wooley, "A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion," IEEE Journal of Solid-State Circuits, vol. 26, no. 12, pp. 1746-1756, Dec. 1991, doi: 10.1109/4.104165.
    [7] S. Kawahito, "Low-Power Design of Pipeline A/D Converters," IEEE Custom Integrated Circuits Conference 2006, 2006, pp. 505-512, doi: 10.1109/CICC.2006.320894.
    [8] Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto, T. Kuroda, "Split capacitor DAC mismatch calibration in successive approximation ADC," 2009 IEEE Custom Integrated Circuits Conference, 2009, pp. 279-282, doi: 10.1109/CICC.2009.5280859.
    [9] W. Mao, Y. Li, C. Heng and Y. Lian, "A Low Power 12-bit 1-kS/s SAR ADC for Biomedical Signal Processing," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 2, pp. 477-488, Feb. 2019, doi: 10.1109/TCSI.2018.2859837.
    [10] Y. Zhu, C. -H. Chan, S. -P. U and R. P. Martins, "An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS," IEEE Journal of Solid-State Circuits, vol. 51, no. 5, pp. 1223-1234, May 2016, doi: 10.1109/JSSC.2016.2522762.
    [11] M. Brandolini, Y. J. Shin, K. Raviprakash, T. Wang, R. Wu, H. M. Geddada, Y. J. Ko. Y. Ding, C. S. Huang, W. T. Shih, M. H. Hsieh, Acer W. T. Chou, T. Li, A. Shrivastava, Dominique Y. C. Chen, Bryan J. J. Hung, G. Cusmai, J. Wu, M.M. Zhang, Y. Yao, G. Unruh, A. Venes, H. S. Huang, C. Y. Chen, "A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS," IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2922-2934, Dec. 2015, doi: 10.1109/JSSC.2015.2464684.
    [12] O. Rajaee, T. Musah, N. Maghari, S. Takeuchi, M. Aniya, K. Hamashita, U. Moon, "Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC," IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 719-730, April 2010, doi: 10.1109/JSSC.2010.2042246.
    [13] S. Li, B. Qiao, M. Gandara, D. Z. Pan and N. Sun, "A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure," IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3484-3496, Dec. 2018, doi: 10.1109/JSSC.2018.2871081.
    [14] M. Kim, S. Hong and O. Kwon, "An Area-Efficient and Low-Power 12-b SAR/Single-Slope ADC Without Calibration Method for CMOS Image Sensors," IEEE Transactions on Electron Devices, vol. 63, no. 9, pp. 3599-3604, Sept. 2016, doi: 10.1109/TED.2016.2587721.
    [15] Y. J. Chen, K. H. Chang and C. C. Hsieh, "A 2.02–5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS," IEEE Journal of Solid-State Circuits, vol. 51, no. 2, pp. 357-364, Feb. 2016, doi: 10.1109/JSSC.2015.2492781.
    [16] T. Oh, H. Venkatram and U. Moon, "A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information," IEEE Journal of Solid-State Circuits, vol. 49, no. 4, pp. 961-971, April 2014, doi: 10.1109/JSSC.2013.2293019.
    [17] S. D. Kulchycki, R. Trofin, K. Vleugels and B. A. Wooley, "A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded Sigma Delta Modulator," IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 796-804, April 2008, doi: 10.1109/JSSC.2008.917499.
    [18] L. Rossi, S. Tanner and P. Farine, "Performance Analysis of a Hybrid Incremental and Cyclic A/D Conversion Principle," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 7, pp. 1383-1390, July 2009, doi: 10.1109/TCSI.2008.2006215.
    [19] B. Murmann, "ADC Performance Survey 1997-2021," [Online]. Available: http://web.stanford.edu/~murmann/adcsurvey.html.
    [20] A. M. A. Ali, H. Dinc, P. Bhoraskar, C. Dillon, S. Puckett, B. Gray, C. Speir, J. Lanford, D. Jarman, J. Brunsilius, P. Derounian, B. Jeffries, U. Mehta, M. McShea, H. Y. Lee, "29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, pp. 482-483, doi: 10.1109/ISSCC.2014.6757522.
    [21] R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, pp. 539-550, April 1999, doi: 10.1109/49.761034.
    [22] Y. Zhu, C. H. Chan, U. F. Chio, S. W. Sin, S. P. U, R. P. Martins, F. Maloberti, "A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS," IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, June 2010, doi: 10.1109/JSSC.2010.2048498.
    [23] B. Verbruggen, M. Iriguchi and J. Craninckx, "A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS," IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2880-2887, Dec. 2012, doi: 10.1109/JSSC.2012.2217873.
    [24] H. Huang, H. Xu, B. Elies and Y. Chiu, "A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation," IEEE Journal of Solid-State Circuits, vol. 52, no. 12, pp. 3235-3247, Dec. 2017, doi: 10.1109/JSSC.2017.2732731.
    [25] F. van der Goes, C. M. Ward, S. Astgimath, H. Yan, J. Riley, Z. Zeng, J. Mulder, S. Wang, K. Bult, "A 1.5 mW 68 dB SNDR 80 Ms/s 2* Interleaved Pipelined SAR ADC in 28 nm CMOS," IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2835-2845, Dec. 2014, doi: 10.1109/JSSC.2014.2361774.
    [26] Seo, M.-J. A Single-Amplifier Dual-Residue Pipelined-SAR ADC. Electronics 2021, 10, 421. https://doi.org/10.3390/ electronics10040421.
    [27] B. Verbruggen, K. Deguchi, B. Malki and J. Craninckx, "A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS," 2014 Symposium on VLSI Circuits Digest of Technical Papers, 2014, pp. 1-2, doi: 10.1109/VLSIC.2014.6858451.
    [28] T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol. 30, no. 3, pp. 166-172, March 1995, doi: 10.1109/4.364429.
    [29] C. Liu, S. Chang, G. Huang, Y. Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010, doi: 10.1109/JSSC.2010.2042254.
    [30] A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999, doi: 10.1109/4.760369.
    [31] P. M. Figueiredo and J. C. Vital, "Kickback noise reduction techniques for CMOS latched comparators," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 7, pp. 541-545, July 2006, doi: 10.1109/TCSII.2006.875308.

    QR CODE