由於電路老化會降低系統效能甚至違反時序使系統故障，因此老化效應已經成了目前多核心系統中要克服的嚴峻挑戰之一。為了改善多核心系統因為老化而帶來的影響，先前的研究都是使用對稱式老化，透過各種工作分配的演算法搭配動態電壓頻率調變，使多核心系統中的所有核心具有相似的老化程度來克服老化效應所降低的系統效能並延長多核心系統的壽命。
雖然對稱式老化能夠有效的容忍老化效應所降低的系統性能，但它可能不適用於某些情況之下。
考慮一個具有緊急時限的工作在系統運行多年後到達，對稱式老化的方法會因為所有核心的老化程度都是一致的關係，導致沒有任何一顆核心能夠使這個工作在時限之內完成，這種無可避免的故障將會縮短系統的壽命。然而，如果在早期的階段能夠讓少數的核心維持在較健康的情形，在後期階段時即使其他剩餘的核心都老化到了一定的程度，這些核心還是能完成緊急時限的工作，將能避免系統故障並延長系統的壽命，這方法稱之為非對稱式老化。
通過以上的觀察，這篇論文提出創新的非對稱式老化的方法來改善多核心系統的可靠度，方法包含工作圖的重新定時，工作分配的排序，非對稱式老化下的工作分配，以及動態電壓調變。藉由這篇論文提出的非對稱式老化，讓多核心系統在所有的壽命階段中能有最大的機會完成緊急時限工作。實驗結果顯示，與磨損感知的方法相比，我們的方法可以將多核心系統的壽命最高增加2.87倍。

Aging effects have become one of the most drastic challenges in modern multi-core systems, which may lead to performance degradation or even timing failure. To tolerance aging effects and extend the lifetime of the system, previous researchers proposed maintaining all cores in the multi-core system under similar aging conditions (symmetric aging) through various task assignment algorithms and/or dynamic voltage frequency scaling.
Although the concept of symmetric aging provides efficient approaches to tolerate aging, it may not be suitable for some situations. If a critical task (i.e., a task with tight timing constraint) arrives when the system has operated for years, it is possible that none of the equivalently aged cores is able to complete the critical task within its timing constraint. This unavoidable timing failure then shortens the lifetime of the system. In contrast, if a few cores are always kept healthy, these cores can be used to execute the critical task even all the other cores are aged (asymmetric aging), which avoids timing failure and extends the system lifetime.
With the above observation, this thesis proposes a novel reliability improvement framework which consists of task graph Retiming, task Ordering, task Assignment under asymmetric aging, and Dynamic voltage selection (ROAD) for multi-core systems. With our framework, the asymmetric aging of cores can maximize the probability to successfully execute critical tasks at all life stages of the system. Experimental results show that our approach can increase the lifetime of a multi-core system up to 2.87x compared to wearout-aware method.

[1] Predictive Technology Model (PTM). http://www.ptm.asu.edu.
[2] M.A. Alam and S. Mahapatra. A comprehensive model of pmos nbti degradation. Microelectronics
Reliability, 45(1):71 – 81, Jan 2005.
[3] M. Basoglu, M. Orshansky, and M. Erez. Nbti-aware dvfs: A new approach to saving
energy and increasing processor lifetime. In 2010 ACM/IEEE International Symposium
on Low-Power Electronics and Design (ISLPED), pages 253–258, Aug 2010.
[4] A. Calimera, E. Macii, and M. Poncino. Nbti-aware sleep transistor design for reliable
power-gating. In Proceedings of the 19th ACM Great Lakes Symposium on VLSI,
GLSVLSI ’09, pages 333–338, July 2009.
[5] K. Chiu, Y. Chen, and I. Lin. An efficient nbti-aware wake-up strategy for power-gated
designs. In 2018 Design, Automation Test in Europe Conference Exhibition (DATE),
pages 901–904, March 2018.
[6] R. P. Dick, D. L. Rhodes, and W. Wolf. Tgff: task graphs for free. In Proceedings of the
Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE’98),
pages 97–101, March 1998.
[7] M. Ebrahimi, F. Oboril, S. Kiamehr, and M. B. Tahoori. Aging-aware logic synthesis. In
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages
61–68, Nov 2013.
[8] J. Fang, S. Gupta, S. V. Kumar, S. K. Marella, V. Mishra, P. Zhou, and S. S. Sapatnekar.
Circuit reliability: From physics to architectures: Embedded tutorial paper. In 2012
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 243–
246, Nov 2012.
[9] A. B. Gabis, P. Bomel, and M. Sevaux. Bi-objective cost function for adaptive routing
in network-on-chip. IEEE Transactions on Multi-Scale Computing Systems, 4(2):177–
187, April 2018.
[10] S. Hamdan and A. Cheaitou. Supplier selection and order allocation with green criteria:
An mcdm and multi-objective optimization approach. Computers & Operations
Research, 81:282 – 304, May 2017.
[11] J. Henkel, L. Bauer, N. Dutt, P. Gupta, S. Nassif, M. Shafique, M. Tahoori, and N. Wehn.
Reliable on-chip systems in the nano-era: Lessons learnt and future trends. In 2013 50th
ACM/EDAC/IEEE Design Automation Conference (DAC), pages 1–10, May 2013.
[12] N. K. Jha, P. S. Reddy, D. K. Sharma, and V. R. Rao. Nbti degradation and its impact for
analog circuit reliability. IEEE Transactions on Electron Devices, 52(12):2609–2615,
Dec 2005.
[13] U. R. Karpuzcu, B. Greskamp, and J. Torrellas. The bubblewrap many-core: Popping
cores for sequential acceleration. In 2009 42nd Annual IEEE/ACM International Symposium
on Microarchitecture (MICRO), pages 447–458, Dec 2009.
[14] P. Mercati, F. Paterna, A. Bartolini, L. Benini, and T. S. Rosing. Dynamic variability
management in mobile multicore processors under lifetime constraints. In 2014 IEEE
32nd International Conference on Computer Design (ICCD), pages 448–455, Oct 2014.
[15] F. Paterna, A. Acquaviva, and L. Benini. Aging-aware energy-efficient workload allocation
for mobile multimedia platforms. IEEE Transactions on Parallel and Distributed
Systems, 24(8):1489–1499, Aug 2013.
[16] B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy. Negative bias temperature
instability: Estimation and design for improved reliability of nanoscale circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
26(4):743–751, April 2007.
[17] D. Shin and J. Kim. Power-aware scheduling of conditional task graphs in real-time
multiprocessor systems. In Proceedings of the 2003 International Symposium on Low
Power Electronics and Design, ISLPED ’03, pages 408–413, Sep 2003.
[18] J. Sun, R. Zheng, J. Velamala, Y. Cao, R. Lysecky, K. Shankar, and J. Roveda. A selftuning
design methodology for power-efficient multi-core systems. ACM Trans. Des.
Autom. Electron. Syst., 18(1):4:1–4:24, January 2013.
[19] A. Tiwari and J. Torrellas. Facelift: Hiding and slowing down aging in multicores. In
2008 41st IEEE/ACM International Symposium on Microarchitecture, pages 129–140,
Nov 2008.
[20] R. Vattikonda, W. Wang, and Y. Cao. Modeling and minimization of pmos nbti effect
for robust nanometer design. In 2006 43rd ACM/IEEE Design Automation Conference,
pages 1047–1052, July 2006.
[21] W. Wang, Z. Wei, S. Yang, and Y. Cao. An efficient method to identify critical gates
under circuit aging. In 2007 IEEE/ACM International Conference on Computer-Aided
Design, pages 735–740, Nov 2007.
[22] C. Xian, Y. Lu, and Z. Li. Dynamic voltage scaling for multitasking real-time systems
with uncertain execution time. IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, 27(8):1467–1478, Aug 2008.
[23] L. Zhang and R. P. Dick. Scheduled voltage scaling for increasing lifetime in the presence
of nbti. In 2009 Asia and South Pacific Design Automation Conference, pages
492–497, Jan 2009.
[24] Y. Zhang, X. Hu, and D. Z. Chen. Task scheduling and voltage selection for energy
minimization. In Proceedings 2002 Design Automation Conference, pages 183–188,
June 2002.