近年來電子產品整合諸多功能性於一身，使得電子產品晶片所需的腳接數增加。覆晶封裝是將佈值於晶片上的錫鉛隆點直接連接於基板上，因為晶片與基板熱膨脹係數的不同，隆點會受到熱應力變化造成剝落毀損。為了增加錫鉛隆點的可靠度，需在晶片與基板之間封膠，調和熱膨脹係數的差異。傳統覆晶封裝需使用兩個步驟，第一步驟使用毛細力將底部封膠充填入晶片與基板之間的空隙，第二步驟使用模封材料進行包覆成型封裝。有別於傳統的覆晶封裝，成型底部填充(MUF) 概念是使用單一步驟來達到底部充填與包覆成型的效果，使得封裝過程能更簡單且更快速。但隨著晶片與基板的空隙逐漸縮小，導致晶片上下方前流不平衡容易造成封包效應的不良產品。在本研究中，我們以數值模擬的方式，模擬不同幾何參數對於填充前流的流場變化。接著以實驗的方式，探討模腔內不同環境參數對於封包的影響，最後找出封裝成功的重要參數。

In recent years, the chip of electronic products asks for more and more I/O ports due to the integration of many functions in one single chip. Flip chip process implants solder bumps on the chip surface and those bumps are directly connected to the substrate. Due to the mismatch of the coefficients of thermal expansion (CTE) between chip and substrate, solder bumps will be subjected to thermal stress in service and that causes damage and delamination. In order to increase the reliability of solder bumps, epoxy molding compound (EMC) is filled into the gap between chip and substrate, to reconcile differences in the thermal expansion coefficients. Traditional flip chip packaging uses a two-step approach. The first step uses the capillary force to fill the gap between chip and substrate, and the second step uses EMC to over mold the package. Unlike traditional flip chip packaging, molded underfill (MUF) concept uses a single step approach to achieve both underfill and over mold at the same time, resulting in a simpler and faster process. In the study, we construct a numerical simulation model to simulate the melt front movement and void formation for different geometric parameters. Then we performed molding experiments to confer the effect on void formation for different environmental parameters in the cavity.

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