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研究生: 王鴻耀
Wang, Hung-yao
論文名稱: UWB低電壓低雜訊放大器及摺疊式與次諧波式混頻器之研究設計
Research on Low-voltage LNA and Folded, Even-harmonic Mixers for UWB Application
指導教授: 莊惠如
Chuang, Huey-ru
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 中文
論文頁數: 78
中文關鍵詞: 超寬頻低雜訊放大器混頻器
外文關鍵詞: Mixer, LNA, UWB
相關次數: 點閱:68下載:9
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  • 本論文研究應用於UWB接收機之前端CMOS RFICs。設計的晶片包含了3-10-GHz低電壓寬頻低雜訊放大器及3-5-GHz寬頻混頻器。其所研製之晶片皆使用國家晶片中心(CIC)提供之標準TSMC CMOS 0.18 µm製程,晶片量测上除了寬頻低雜訊放大器使用on-wafer方式進行量測之外,其餘的晶片皆打鎊線至PCB板上量測。
    3-10-GHz低電壓寬頻低雜訊放大器利用雙回授式放大器及緩衝放大器的方式得到寬頻訊號放大之特性。設計上利用了增益圓之圖形法實現寬頻增益平坦度,對於電路設計者而言,此方法提供了一個簡單又省時的寬頻放大器實現方式。量測結果顯示,增益為6.9-10.46 dB、雜訊指數為4.71-5.92 dB、input P1dB為-8.5- -2.0 dBm、IIP3為7.5-11.9 dBm。
    3-5-GHz寬頻混頻器晶片可以分成兩部份:(1)摺疊式混頻器,主要是提出一個適用於低電壓操作之寬頻混頻器。為了不讓低電壓操作影響了混頻器的特性,其轉導級部分採用CMOS反相器架構,透過PMOS電晶體來提高增益及線性度。此外,利用shunt-peaking的方法增加操作頻寬。量測顯示,Band 1頻段內的轉換增益為3-8.7 dB、input P1dB為-19.5- -13.5 dBm、IIP3為-10.7- -2.35 dBm。Band 2頻段內的轉換增益為2.3-7.6 dB、input P1dB為-18- -13.5 dBm、IIP3為-5.35- -0.65 dBm。Band 3頻段內的轉換增益為2.9-3.9 dB、input P1dB為-15- -10.5 dBm、IIP3為-4- -1 dBm。(2)次諧波式混頻器,藉由將LO訊號的頻率減半,消除直接降頻接收機之自我混頻效應。同時,利用gm-boosting的差動轉導架構,實現低功率混頻器。量測顯示,Band 1頻段內的轉換增益為1.42-5.76 dB、input P1dB為-17- -15 dBm、IIP3為-10.71- -3.4 dBm。Band 2頻段內的轉換增益為0.98-4.35 dB、input P1dB為-16- -11.5 dBm、IIP3為-10.33- -0.68 dBm。Band 3頻段內的轉換增益為1.1-3.0 dB、input P1dB為-15- -12 dBm、IIP3為-9.87- -0.16 dBm。

    This thesis presents the research on applications of CMOS RFICs for UWB receiver. The first part presents 3-10-GHz low-voltage broadband CMOS low noise amplifier, the second part is 3-5-GHz broadband CMOS folded mixer, and the third part is 3-5-GHz broadband CMOS even-harmonic mixer. The chips are fabricated by a TSMC standard 0.18-μm CMOS process offered by National Chip Implementation Center (CIC) is adopted. The RFICs applied to 3-5-GHz mixer is measured on FR-4 PCB, and 3-10-GHz LNA is on wafer.
    3-10-GHz low-voltage broadband CMOS LNA is the combination of a dual feedback amplifier and a buffer. A dual feedback broadband gain stage is based on graphical method. This method saves time for circuit designer. Measured results show a gain of 6.9-10.46 dB, noise figure of 4.71-5.92 dB, input P1dB of -8.5- -2 dBm, and IIP3 of 7.5-11.9 dBm.
    3-5-GHz broadband CMOS folded mixer is based on Gilber-type mixer. The transconductor stage used CMOS inverter amplifier in order to operate low voltage, and the shunt-peaking technique is used to improve its bandwidth. Measured results show a conversion gain of 2.3-8.7 dB, input P1dB of -19.5- -10.5 dBm, and IIP3 of -10.7- -0.65 dBm.
    3-5-GHz broadband CMOS even-harmonic mixer is based on double balance active mixer. The gm-boosting method saves power for this mixer. Measured results show a conversion gain of 0.98-5.76 dB, input P1dB of -17- -11.5 dBm, and IIP3 of -10.71- -0.16 dBm.

    第一章 緒論 1 1.1 UWB研究背景 1 1.2 UWB定義 2 1.3 UWB發展概況 3 1.4 UWB系統頻帶規劃與系統架構簡介 4 1.5 論文架構 5 第二章 3-10-GHz低電壓寬頻CMOS低雜訊放大器 (TSMC 0.18 μm) 7 2.1 低雜訊放大器簡介 7 2.2 低雜訊放大器雜訊來源 8 2.3 寬頻低雜訊放大器介紹 10 2.4 3-10-GHz低電壓寬頻CMOS低雜訊放大器 13 2.5 低電壓寬頻CMOS低雜訊放大器設計流程 19 2.6 模擬與量测結果 23 2.7 問題與討論 26 第三章 3-5-GHz寬頻摺疊式CMOS混頻器 (TSMC 0.18 μm) 27 3.1 混頻器簡介 27 3.2 混頻器的種類 29 3.3 3-5-GHz寬頻CMOS摺疊式混頻器 33 3.4 寬頻CMOS摺疊式混頻器之設計流程 42 3.5 模擬與量測結果 44 3.6 問題與討論 50 第四章 3-5-GHz寬頻CMOS次諧波混頻器 (TSMC 0.18 μm) 53 4.1 次諧波混頻器之簡介 53 4.2 次諧波混頻原理 55 4.3 3-5-GHz寬頻CMOS次諧波混頻器之實現 57 4.4 次諧波混頻器設計流程 63 4.5 模擬結果 66 4.6 問題與討論 72 第五章 結論 73 參考文獻 75

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