固態硬碟 (SSD) 在許多的消費式電子系統裝置上，已經漸漸取代傳統式的磁帶儲存裝置。一個固態硬碟最主要的優勢是它的平行化架構，其中包含了多個快閃記憶體 chip和 plane 以及多個內部連接的傳輸 bus。而傳統的快閃轉譯層只是設計給單一快閃記憶體 chip，與之不同的是，當快閃轉譯層要使用在固態硬碟上時，必須考慮如何同時的利用到所有的快閃記憶體 chip 和傳輸 bus。
Log-buffer based 的快閃轉譯層 (混合式快閃轉譯層) 已經廣泛的運用在那些中低階的固態硬碟上，由於它們並沒有相當多的記憶體配備在裝置上。雖然在固態硬碟上使用 hybrid mapping 快閃轉譯層比起使用 page-level mapping的快閃轉譯層可以節省出更快的記憶體空間給 buffer cache ，但是當我們追求 SSD的平行度時，前者容易因為 chip 間或是 plane 間的資料搬移而造成較高的回收成本。為了解決這個問題，在這一篇論文中，我們提出了一個如何放置更新資料的策略 (log block 配置策略) 和一個介於 FTL 與 buffer management 的軟體層共同合作機制。這個機制可以提高 SSD 的平行化程度，並且同時地降低回收成本。我們的實驗顯示這樣的設計可以改進 request 的反應時間最高達到五倍的速度，同時大量的降低回收成本。

Solid State Disks (SSDs) have been replacing the conventional magnetic storage devices in many consumer electronic systems. One of the main advantages of SSDs is their parallel architecture consist of multiple flash chips, planes and internal buses. Unlike traditional flash translation layers for single flash memory chip, the FTL for a SSD must utilize the concurrency of the multiple chips and buses as possible.
Log-buffer based flash translation layer (Hybrid mapping FTL) is widely employed on low-end and even middle-end solid-state drives (SSDs) which equip insufficient on-board memory. Although adopting hybrid mapping FTL on SSDs can release much memory space for buffer cache than that used by page-level mapping FTL, its cleaning cost may be much higher due to cross-chip live page copy and inter-plane live page copy while chasing parallelism. To address the problems, in this paper, we suggested an update page placement policy (log-block allocation policy) and a software layer cooperation mechanism between FTL and buffer management to maximize the degree of parallelism while alleviating the cleaning cost at the same time. We run trace-driven simulations to verify our design and the simulation shows that it improved the requests response time up to about 5 times compared to existing policies and reduced the cleaning cost significantly.

[1] N. Agrawal, et al., "Design tradeoffs for SSD performance," 2008, pp. 57-70.
[2] A. Ban, "Flash File System," U.S. Pat. No. 5,404,485, 1995.
[3] A. Ban and R. Hasharon, "Flash File System Optimized for Page-Mode Flash Technologies," U.S. Pat. No. 5,937,425, 1999.
[4] J. S. Bucy, J. Schindler, S. W. Schlosser, and G. R. Ganger, “The disksim simulation environment version 4.0,” Tech. Rep. CMUPDL-08-101, May 2008.
[5] Li-Pin Chang , Tei-Wei Kuo, An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems, Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02), p.187, September 25-27, 2002.
[6] H. Cho, et al., "KAST: K-Associative Sector Translation for NAND Flash Memory in Real-Time Systems," presented at the EDAA, 2009.
[7] L. Chang, "A Hybrid Approach to NAND-Flash-Based Solid-State Disks," IEEE Transactions on Computers, pp. 1-1, 2010.
[8] C. Dirik and B. Jacob, “The performance of pc solid-state disks (ssds) as a function of bandwidth, concurrency, device architecture, and system organization,” in International Symposium on ComputerArchitecture (ISCA), June 2009, pp. 279–289.
[9] Intel Corporation, "Understanding the Flash Translation Layer (FTL) Specification," Application Note AP-684, Dec. 1998.
[10] Intel Corporation, "Software Concerns of Implementing a Resident Flash Disk".

[11] Intel Corporation, "FTL Logger Exchanging Data with FTL Systems".
[12] Iozone. A filesystem benchmark tool http://www.iozone.org
[13] H. Jo, J.U. Kang, S.Y. Park, J.S. Kim, and J. Lee., "FAB: Flash-Aware Buffer Management Policy for Portable Media Players," IEEE Trans. Consumer Electronics, vol. 52, no. 2, pp.485-493, May 2006.
[14] J. Kim, et al., "A SPACE-EFFICIENT FLASH TRANSLATION LAYER FOR COMPACTFLASH SYSTEMS," IEEE transaction, 2002.
[15] J.U. Kang, H. Jo, J.S. Kim, and J. Lee, "A Superblock-based Flash Translation Layer for NAND Flash Memory," Proc. Sixth ACM and IEEE Int’l Conf. Embedded Software, pp. 161-170, 2006.
[16] J. U. Kang, J. S. Kim, C. Park, H. Park, J. Lee, "A multi-channel architecture for high-performance NAND flash-based storage system", Journal of Systems Architecture: the EUROMICRO Journal, vol.53 no.9, p.644-658, September, 2007.
[17] H. Kim and S. Ahn, "BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage," Proc. Sixth USE-NIX Conf. File and Storage Technologies, pp. 239-252, 2008.
[18] S.W. Lee, D.J. Park, T.S. Chung, D.H. Lee, S. Park, and H.J. Song, "A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation," ACM Trans. Embedded Computing Systems, vol. 6, no. 3, article no. 18, Jul. 2007.
[19] S. Lee, et al., "LAST: locality-aware sector translation for NAND flash memory-based storage systems," ACM SIGOPS Operating Systems Review, vol. 42, pp. 36-42, 2008.
[20] H. Lee, et al., "HFTL: Hybrid Flash Translation Layer based on Hot Data Identification for Flash Memory," IEEE Transactions on Consumer Electronics, vol. 55, pp. 2005-2011, 2009.
[21] S. Lim, et al., "FASTer FTL for Enterprise-Class Flash Memory SSDs," 2009.
[22] C. Park, et al., "A re-configurable FTL architecture for NAND flash-based applications," ACM Trans. Embedded Computing Systems,, vol. 7, no. 4, article no. 38, Jul. 2008.
[23] S Park, et al., "CFLRU: A Replacement Algorithm for Flash Memory" Computational Science and Its Applications – ICCSA 2007 (2007),
[24] S Park, et al., "Design and Analysis of Flash Translation Layers for Multi-Channel NAND Flash-based Storage Devices" IEEE Transactions on Consumer Electronics, vol. 55, pp.1392-1400, 2009
[25] S. Park, et al., "Exploiting Internal Parallelism of Flash-based SSDs," IEEE Computer Architecture Letters, 2010.
[26] V. Prabhakaran and T. Wobber. SSD extension for DiskSim simulation environment. http://research.microsoft.com/enus/downloads/b41019e2-1d2b-44d8-b512-ba35ab814cd4/default.aspx
[27] J. Shin, et al., "FTL design exploration in reconfigurable high-performance SSD for server applications," 2009, pp. 338-349.
[28] Samsung Corporation. K9XXG08XXM Flash Memory Specification. http://www.samsung.com/global/system/business/semiconductor/product/2007/6/11/NANDFlash/SLC_LargeBlock/8Gbit/K9F8G08U0M/ds_k9f8g08x0m_rev10.pdf, 2007
[29] SQLsim. A SQL server simulator http://support.microsoft.com/kb/231619