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研究生: 曾偟銘
Tseng, Huang-Ming
論文名稱: RDL封裝製程可靠度驗證與明膠添加對電鍍銅接合界面分析
Investigation of Reliability on RDL Packaging Processes and Analysis of Gelatin Additives by Interface of Electroplated Copper
指導教授: 何青原
Ho, Ching-Yuan
學位類別: 碩士
Master
系所名稱: 工學院 - 機械工程學系
Department of Mechanical Engineering
論文出版年: 2026
畢業學年度: 114
語文別: 中文
論文頁數: 170
中文關鍵詞: 重佈線層(RDL)Via Chain電致遷移Black's Equation電鍍銅明膠(Gelatin)添加劑EBSD殘留應力
外文關鍵詞: Redistribution Layer (RDL), Via Chain, Electromigration, Black's Equation, Electroplated Copper, Gelatin Additive, EBSD, Residual Stress
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  • 本研究旨在探討先進封裝重佈線層(RDL)結構之電致遷移可靠度,並深入分析明膠(Gelatin)添加劑與電鍍液配方對電鍍銅微觀組織及其對銅對銅(Cu-Cu)直接接合界面特性之影響。研究動機源於異質整合趨勢下,線路微縮引發嚴峻的電遷移與固態焊接之界面接合分析。
    在RDL晶片與可靠度驗證方面,本研究利用銅鑲嵌製程(Copper Single Damascene process)於矽晶圓上建構包含單層導線(Metal 1)、導孔(Via)與第二層導線(Metal 2)之多層互連結構,並設計不同尺寸之導孔鏈(Via Chain)作為測試單元。透過加速生命測試(ALT),在設定之恆溫環境下施加高密度直流電流(1×106 A/cm2),以誘發電遷移失效行為。實驗結果發現,不同幾何結構因電流擁擠(Current Crowding)與焦耳熱效應之差異[1],呈現迥異的失效模式,並藉此建立平均失效時間(MTTF)與失效活化能(Ea)之評估流程,完成RDL綜合電路之可靠度壽命分析[2, 3]。
    在材料特性調控與接合分析階段,本研究透過調整電鍍液硫酸濃度(20、50、80g/L)[4]與明膠添加劑(40 ppm)之交互作用[5-8],探討其對銅膜物理性質之影響[9]。依循標準半導體製程規範,試片於電鍍完成後均進行真空熱退火處理以穩定微觀組織,分析顯示,明膠之加入雖能細化晶粒,亦顯著改變材料之物理特性。量測數據證實,隨明膠添加量增加,銅膜硬度由純銅之100-120HV大幅飆升至200 HV以上,呈現近乎一倍的顯著增長,且伴隨劇增的殘留應力;此外,高密度晶界引發的電子散射效應亦造成電阻率上升。實驗進一步觀察到,藉由製程中的熱退火步驟,能有效驅動晶粒成長並釋放應力,使硬度適度降低以優化結構穩定性,提升材料電性,降低殘留應力[10-12]。
    最後進行銅對銅熱壓接合(TCB)實驗,並透過SEM與EBSD觀測界面狀況。實驗數據顯示,由於添加劑使晶粒細化的同時也會生成的小角度晶界(SAGBs)在熱壓過程中發生快速消除與重組,此內部結構演變與界面癒合過程產生動力學競爭,導致原子擴散能量優先消耗於內部小角度晶界結構而無法集中在界面接合,導致界面處存在明顯的殘留孔洞(Voids)與不連續面,大幅縮減了有效導通面積[13]。接合後之電性量測顯示,反映整體互連品質的連鎖電阻隨明膠添加量增加而顯著飆升,此劣化現象直接歸因於接合界面品質不良、介面孔洞率過高,以及材料本身電阻率升高之綜合影響。
    綜上所述,本研究完整釐清了先進封裝RDL構之電遷移失效機制,並證實電鍍液配方對銅膜物性與接合品質具有決定性影響。實驗顯示,雖然明膠添加劑配合硫酸濃度調整能產生較高(111)優選取向,但亦不可避免地導致硬度倍增、應力劇增及電性劣化等負面效應。透過製程中熱退火步驟之優化,雖能有效緩解電性與力學性質之負擔,但明膠所引發的小角度晶界顯著抑制了Cu-Cu接合時的原子擴散,導致界面孔洞生成與連鎖電阻飆升[14]。本研究之成果不僅建立了一套RDL壽命評估模型,更針對銅在製程中的優劣權衡提供了關鍵量化數據,為未來開發低損耗、高可靠度之異質整合封裝技術提供重要參考依據。

    This study presents a comprehensive investigation into the electromigration reliability of multi-layer interconnects in advanced redistribution layers (RDL) and quantifies the impacts of gelatin additives and electrolyte optimization on the microstructural transition, mechanical stability, residual stress, and subsequent low-temperature copper-to-copper (Cu-Cu) direct thermal compression bonding (TCB). Driven by the rapid downsizing of circuit dimensions in heterogeneous integration, these interconnect topologies must withstand extreme current densities and thermal stresses. By utilizing the single-damascene process at the Taiwan Semiconductor Research Institute (TSRI), multi-layer circuits consisting of single traces (Metal 1), single vias, and via chains were successfully validated via precise ohmic characterization, isolating robust baseline via contact resistivities of 16 and16.7Ω·um2. Accelerated life testing under high-density direct current demonstrated distinct geometric-dependent failure modes driven by localized current crowding and Joule heating, where the extracted activation energy dropped significantly from 0.87up eV for Metal 1 to 0.62eV for the via chain, proving that RDL reliability is fundamentally bottlenecked by the vertical via junctions rather than bulk planar metallurgy.
    Simultaneously, the correlation between electroplating bath components and material microstructural inheritance was quantified. The inclusion of 40 ppm gelatin as a crystal suppressor induced drastic grain refinement and reduced texture alignment under a high deposition current density of 80mA/cm2, which exponentially increased the copper film hardness to over 200 HV and locked in high-density kernel average misorientation (KAM) micro-strains. However, this refinement caused the initial in-plane tensile residual stress to surge beyond 110 MPa, posing a severe warpage risk for advanced packaging substrates. By optimizing the thermal budget through vacuum annealing at 300°C for 30 minutes, the stored strain energy within the suppressed matrix acted as a powerful driving force for structural reordering, safely relaxing the planar residual stress by over 40% to 65 MPa while maximizing the preferential (111)/(200) texture ratio to an exceptional value of 10.05.
    Finally, direct Cu-Cu TCB was executed at 300°C and 50 MPa for 1 hour to evaluate interface evolution. Microstructural characterization via SEM and EBSD revealed an unusual phenomenon where the gelatin-modified fine-grained structures possessed a 2.5- to 4.5-fold higher density of initial low-angle grain boundaries (LAGBs, 2°–15°) before bonding. During the TCB sequence, the rapid annihilation and structural reconfiguration of this massive internal sub-grain network established a severe kinetic competition against the atomic diffusion healing process at the contact interface. Consequently, the system's thermal activation energy was preferentially consumed to reorganize the unstable bulk matrix internally rather than driving long-range atomic diffusion across the contact seam, leaving continuous arrays of micro-voids trapped along the bonding line. This interface degradation induced a heavy constriction resistance, causing the post-bond sheet resistance to spike dramatically to 24mΩ/sq, whereas the conventional coarse-grained structure successfully directed thermal energy to the joint plane, achieving complete across-interface grain growth with a minimal electrical resistance of 8mΩ/sq.

    摘要 I EXTENDED ABSTRACT III 目錄 XI 表目錄 XIII 圖目錄 XV 第1章 緒論 1 1.1 前言 1 1.2 研究動機與目的 2 第2章 文獻回顧 3 2.1 三維積體電路封裝簡介 3 2.2 銅重佈線層在可靠度的挑戰 7 2.3 電遷移效應 10 2.4 奈米雙晶銅簡介 13 2.5 直流電鍍液中之添加劑 16 2.6 銅薄膜殘留應力 18 2.7 金屬直接接合 22 第3章 實驗步驟與方法 24 3.1 實驗流程 24 3.2 試件製備 26 3.2.1. 光罩設計(5″Design Rule) 26 3.2.2. RDL晶片製作(Process Flow)與封裝 34 3.2.3. 製備與退火電鍍銅 48 3.2.4. 直接熱壓接合與接合界面分析 50 3.3 電性量測與電致遷移 54 3.4 電鍍銅-電流效率分析 56 3.5 微觀結構分析 58 3.5.1 掃描式電子顯微鏡與EBSD分析 58 3.5.2 X光繞射分析 58 3.5.3 殘留應力分析 58 3.6 電性量測-薄膜電阻 59 3.7 微小試硬度分析 60 第4章 結果與討論 63 4.1 RDL晶片可靠度驗證 63 4.1.1. Metal 1電性量測 63 4.1.2. Single Via電性量測 68 4.1.3. Via Chain電致遷移 78 4.1.4. Metal 1電致遷移 86 4.1.5. 活化能與RDL失效位置 91 4.2 電鍍銅性質分析 93 4.2.1. 電鍍銅-電流效率 93 4.2.2. 電鍍銅XRD分析 95 4.2.3. 電鍍銅SEM分析 101 4.2.4. 電鍍銅EBSD 103 4.2.5. 電鍍銅-薄膜電阻 115 4.2.6. 電鍍銅-硬度 117 4.2.7. 電鍍銅-殘留應力分析 120 4.3 熱壓接銅性質分析 122 4.3.1. 熱壓接銅橫截面SEM分析 122 4.3.2. 熱壓接銅EBSD 124 4.3.3. 熱壓接銅接合機制 133 4.3.4. 熱壓接銅薄膜電阻 135 第5章 結論 137 第6章 未來研究方向 139 第7章 參考文獻 141

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