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研究生：	陳建凱 Chen, Jian-Kai
論文名稱：	InAlN/GaN HEMT元件中源-汲極距與閘-源極重疊結構搭配源-汲極圖案化蝕刻之電性探討 Investigation of Source-Drain Spacing and Gate-Source Overlap Structures combined with Patterned Source-Drain Etching in InAlN/GaN HEMTs
指導教授：	蘇炎坤 Su, Yan-Kuin 莊文魁 Chuang, Wen-Kuei
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 奈米積體電路工程碩士博士學位學程 MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年：	2026
畢業學年度：	114
語文別：	英文
論文頁數：	111
中文關鍵詞：	高電子遷移率場效電晶體、源極與汲極距離縮減、重疊結構、圖案化蝕刻
外文關鍵詞：	high electron mobility transistor, LSD scaling effect, Overlap structure, patterned recess
相關次數：	點閱：66 下載：5
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本研究探討源極和汲極距離(LSD)縮減對電性的變化以及確認閘極重疊汲極結構是否可行。實驗一製作閘極置中在源極與汲極(Middle gate)和閘極重疊在汲極(Overlap gate)兩種不同的結構，且兩種結構的源極和汲極距離有逐漸縮減，Middle gate結構中從10 μm縮減為8 μm最後到6 μm，而Overlap gate結構中從6 μm縮減為5 μm最後到4 μm。
　實驗二是在實驗一中導入於源極與汲極金屬沉積前進行的阻擋層圖案化蝕刻（patterned recess）製程，以進一步探討其對元件是否會有更佳的電性，實驗一與實驗二探討的電性以最大電流密度和導通電阻為主。
　實驗一結果顯示，兩種結構中源極和汲極距離縮減對最大電流密度有增加的趨勢而導通電阻有下降的趨勢，且也確認了閘極重疊在汲極的結構是可行的。Middle gate結構中LSD縮減至6 μm時，最大電流密度增加至384.47 mA/mm，導通電阻下降至7.14 Ω-mm。Overlap gate結構中LSD縮減至4 μm時，最大電流密度增加至487 mA/mm，導通電阻下降至5.63 Ω-mm。
　實驗二結果顯示，源極和汲極距離縮減依然對最大電流密度有增加的趨勢而導通電阻有下降的趨勢，且因導入圖案化蝕刻（patterned recess）對最大電流密度和導通電阻較於實驗一有更佳的表現。Middle gate結構中LSD為6 μm時，最大電流密度增加至456.56 mA/mm，導通電阻下降至6.01 Ω-mm。Overlap gate結構中LSD為4 μm時，最大電流密度增加至561.92 mA/mm，導通電阻下降至4.88 Ω-mm。

This research explores the electrical variations induced by reducing the source-drain distance (LSD) and assesses the viability of a gate-overlapped drain structure. In Experiment I, centered-gate (Middle-gate) and gate-overlapped (Overlap-gate) structures were fabricated. The LSD for both configurations was systematically decreased: from 10 μm to 8 μm to 6 μm for the Middle-gate structures, and from 6 μm to 5 μm to 4 μm for the Overlap-gate structures.
　Experiment II introduces a patterned recess etching step before source/drain metal deposition into the process flow established in Experiment I to investigate potential electrical improvements. Across both experiments, the primary electrical metrics evaluated are the maximum current density (ID(max) ) and the on-resistance (Ron).
　According to the electrical characterization results of Experiment I, the systematic reduction of the source-to-drain spacing (LSD) introduced a beneficial scaling effect, characterized by an upward trend in the maximum current density and a downward trend in the on-resistance (Ron) for both geometries. Crucially, the structural feasibility of the gate-overlapped-on-drain (Overlap-gate) architecture was successfully confirmed. In the case of the Middle-gate structure, shortening the LSD to 6m elevated the maximum current density to 384.47 mA/mm and lowered the on-resistance to 7.14 Ω-mm. Most notably, the Overlap-gate structure with an LSD of 4 μm exhibited superior performance, achieving an enhanced maximum current density of 487 mA/mm and a reduced on-resistance of 5.63 Ω-mm.
　Experiment II results indicate that reducing the source-to-drain distance (LSD) still leads to a higher maximum current density and a lower on-resistance (Ron). Furthermore, due to the implementation of the patterned recess, both electrical parameters showed improved performance over the outcomes in Experiment I. At an LSD of 6 μm in the Middle-gate structure, the maximum current density rose to 456.56 mA/mm and the on-resistance fell to 6.01 Ω-mm. For the Overlap-gate structure at an LSD of 4 μm, the maximum current density was boosted to 561.92 mA/mm while the on-resistance further decreased to 4.88 Ω-mm.

中文摘要	I
Abstract	III
Acknowledgement	V
CONTENTS	VI
List of Tables	IX
List of Figures	XI
Chapter 1 Introduction	1
1-1 Background	1
1-2 Motivation	3
Chapter 2 Literature Review of nitride-based HEMTs	5
2-1 Standard Heterostructure of GaN-Based HEMTs	5
2-2 Advantages of InAlN/GaN HEMTs	7
2-3 Spontaneous Polarization	8
2-4 Piezoelectric Polarization	9
2-5 Physical Origin of the 2DEG Channel	11
2-6 Fundamentals of Metal-Semiconductor Interfaces	13
     2-6-1 Ohmic contact	13
     2-6-2 Transmission line model	15
2-7 Characterization of HEMTs	17
     2-7-1 Threshold Voltage	17
     2-7-2 Current On/Off Ratio	18
     2-7-3 Transconductance	18
     2-7-4 Subthreshold Swing	19
Chapter 3 Experimental details	20
3-1 Experimental Equipment	20
     3-1-1 Spin Coater	20
     3-1-2 Mask Aligner	21
     3-1-3 ICP-RIE	22
     3-1-4 Electron Beam Evaporation System	23
     3-1-5 Rapid Thermal Annealing System	24
     3-1-6 Atomic Layer Deposition System	25
     3-1-7 B1500A Electrical Measurement	26
3-2 Fabrication of Middle and Overlap gate HEMTs	27
     3-2-1 Sample cleaning	28
     3-2-2 Mesa isolation	29
     3-2-3 Ohmic contact	31
     3-2-4 Dielectric	33
     3-2-5 Gate electrode	34
     3-2-6 Passivation	35
     3-2-7 Via	36
3-3 Fabrication of Middle and Overlap gate HEMTs with patterned Source-Drain etching	38
     3-3-1 Sample cleaning	39
     3-3-2 Mesa isolation	40
     3-3-3 Patterned Source-Drain recess	41
     3-3-4 Ohmic contact	43
     3-3-5 Dielectric	45
     3-3-6 Gate electrode	46
     3-3-7 Passivation	47
     3-3-8 Via	47
Chapter 4 Comparison of Middle and Overlap gate structure	49
4-1 Middle gate structure (LGS＝4μm、LG＝2μm、	LGD＝4μm)	49
4-2 Middle gate structure (LGS＝3μm、LG＝2μm、	LGD＝3μm)	52
4-3 Middle gate structure (LGS＝2μm、LG＝2μm、	LGD＝2μm)	54
4-4 Overlap gate structure (LGS＝25 nm、LG＝2μm、LGD＝4μm)	56
4-5 Overlap gate structure (LGS＝25 nm、LG＝2μm、LGD＝3μm)	59
4-6 Overlap gate structure (LGS＝25 nm、LG＝2μm、LGD＝2μm)	62
4-7 Summary	65
Chapter 5 Comparison of Middle and Overlap gate structure with patterned recess	68
5-1 Middle gate structure (LGS＝4μm、LG＝2μm、	LGD＝4μm)	68
5-2 Middle gate structure (LGS＝3μm、LG＝2μm、LGD＝3μm)	71
5-3 Middle gate structure (LGS＝2μm、LG＝2μm、	LGD＝2μm)	74
5-4 Overlap gate structure (LGS＝25 nm、LG＝2μm、LGD＝4μm)	76
5-5 Overlap gate structure (LGS＝25 nm、LG＝2μm、LGD＝3μm)	79
5-6 Overlap gate structure (LGS＝25 nm、LG＝2μm、LGD＝2μm)	82
5-7 Summary	85
Chapter 6 Conclusion	88
Chapter 7 Future work	90
Chapter 8 Reference	92
                                    

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