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研究生: 蔡凱瑞
Tsai, Kai-Ruei
論文名稱: 運用FPGA實現脈動陣列以提高移動目標物偵測之幀率
The Implementation of Systolic Arrays with FPGA to Increase Frame Rates for Moving Target Detection
指導教授: 田思齊
Tien, Szu-Chi
學位類別: 碩士
Master
系所名稱: 工學院 - 機械工程學系
Department of Mechanical Engineering
論文出版年: 2023
畢業學年度: 111
語文別: 中文
論文頁數: 53
中文關鍵詞: 脈動陣列FPGA區塊比對法隨機取樣一致算法(RANSAC)
外文關鍵詞: Systolic Array, FPGA, Block matching method, Random Sample Consensus(RANSAC)
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  • 本研究是建立一個基於FPGA平台的系統,以用於移動取像裝置之實時標記移動目標物。從取樣頻率為26Hz的相機獲取影像後,使用脈動陣列架構對連續兩幀影像進行區塊比對,以完成影像配準。接著利用隨機取樣一致算法找出最適合的背景位移仿射變換模型。最後,我們利用已經完成背景位移補償的兩張影像進行幀間差法,以確定移動的物體並完成對移動物體的標記。整個系統的流程包括影像的獲取、區塊比對、仿射變換模型推導以及最終之移動物體標記。研究結果顯示,相較於傳統之序列式運算,以脈動陣列架構進行之區塊比對有利於電路對平行運算之實現,同時達到節省運算元件的效果。

    This research is to build a system based on an FPGA platform for real-time marking of moving objects in portable imaging devices. After capturing images from a camera with a sampling frequency of 26Hz, a systolic array architecture is used to perform block matching on two consecutive frames of images to access image registration. And using RANdom SAmple Consensus(RANSAC) to find the most suitable background displacement affine transformation model. Finally, using the frame differencing method on the two images with background displacement compensation to determine the moving object and complete the marking of the moving object. The entire research includes image acquisition, block matching, derivation of affine transformation models, and marking of moving objects. The results show that compared to traditional sequential computations and the systolic array architecture for block matching. The systolic array is more suitable for parallel computation in the circuit design and reduces computational elements.

    摘要 i Extend Abstract ii 致謝 vii 圖目錄 x 表目錄 xii 符號表 xiii 第一章 緒論 1 第二章 脈動陣列之區塊比對 4 2.1 區塊比對法概念與通式 4 2.2 脈動陣列簡介 6 2.3 脈動陣列範例 9 2.3.1 樣板大小為2 × 2的例子 9 2.3.2 樣板大小為8 × 8的例子 13 第三章 整體實驗架構 17 3.1 演算流程 17 3.1.1 影像擷取(Image Capturing) 19 3.1.2 移動相機估測(Camera motion estimation) 22 3.1.3 移動物體偵測(Moving target detection) 25 3.2 硬體架構說明 33 第四章 實驗結果與討論 38 4.1 單元前置驗證 38 4.2 實驗條件 42 4.2.1 建立時間與保持時間 42 4.2.2 硬體參數 43 4.2.3 演算法參數 44 4.3 實驗結果與討論 46 第五章 結論與未來展望 50 5.1 結論 50 5.2 未來展望 50 參考文獻 51

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