本論文研製應用於毫米波94-GHz CMOS射頻前端收發機之47-GHz CMOS壓控振盪器及鎖相迴路晶片，皆採用TSMC CMOS 90-nm GUTM製程設計實現。高輸出功率與寬可調頻寬之94-GHz CMOS雙推式壓控振盪器以雙推式的概念，利用電路本身的諧波訊號達成倍頻效果，並在共模點輸出二倍頻(94-GHz)之諧波訊號，如此便能在較為低頻、元件特性較好的條件下完成振盪核心設計，產生響應較好的高頻訊號。使用轉導值提升技巧之47-GHz CMOS壓控振盪器在電路設計上使用上下雙層纏繞的變壓器形式電感，設置於交互耦合對電晶體之汲極與閘極處，使其產生轉導值提升的效果，並以公式推導佐證，該技巧確實可改善轉導值不足的問題，減輕高頻電路之設計負擔。47-GHz CMOS毫米波鎖相迴路射頻晶片之電路架構包含47-GHz壓控振盪器、注入鎖定除頻器、電流邏輯模式除頻器、真實單相時脈除頻器、相位頻率偵測器、電荷幫浦以及迴路濾波器等部分，其中壓控振盪器利用轉導值提升技巧完成設計，注入鎖定除頻器則是利用forward-body-bias、dual-mixing及series picking等技術改善鎖定頻寬問題完成設計，其他子電路亦經過良好的設計，藉此得到比單一振盪器電路更為穩定精準之訊號輸出，減少系統整合運作時的誤差。電路設計使用Agilent ADS進行模擬，走線效應則使用Ansys 3-D全波電磁模擬軟體HFSS進行模擬。晶片採用fully on-wafer與wafer mounted on PCB的方式進行量測。

This thesis presents the design research on a 94-GHz millimeter-wave CMOS voltage controlled oscillator (VCO), 47-GHz VCO and phase locked loop (PLL) for a 94-GHz CMOS RF front-end transceiver. These chips are implemented by TSMC 90-nm CMOS process. In the 94-GHz VCO design, the push-push frequency doubling technique is adopted to overcome the process limitation and have better performance. In the 47-GHz VCO design, a gm-boost technique is adopted for better star-up condition at high frequency design. In the 47-GHz PLL, the gm-boost technique is adopted in VCO circuit. The forward body bias, dual-mixing, and series-peaking techniques are adopted in injection locked frequency divider for wider locking range. The other sub-circuits of PLL are also well designed. The simulated and measured results of the designed RFICs are compared and discussed in this thesis.

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