隨著電子封裝朝輕薄短小及高功率方向發展，覆晶封裝（flip-chip）正符合輕巧、高I/O密度、高傳輸速度等優點，使得此類電子產品需求與日俱增。在朝高功率發展條件下，因銲錫接點肩負訊號傳遞與結構支撐的重要角色，且由於銲錫接點及相連金屬導線尺寸與電阻上的差異，導致流經銲錫接點的電流密度急遽昇高，此電流擁擠效應及衍生的焦耳熱將衝擊銲錫接點電遷移（electromigration）的可靠度。本研究針對銲錫接點結構在電流及溫度作用下，異質材料間所發生的界面反應、擴散機制及所衍生的破壞模式來加以探討。電遷移效應為一耦合場分析（coupled-field analysis）問題，包含電-熱-應力耦合作用下所驅動的質傳問題。本文將分三個階段來進行，第一階段為實驗觀察銲錫接點在不同電流密度及溫度作用下的反應情況；第二階段進行三維有限元素的電熱耦合分析，並比對實際量測晶片表面溫度以驗證模擬分析的準確性；第三階段藉由模擬銲錫接點的電流擁擠因子及最高溫度修正了更精確的電遷移可靠度模型之疲勞壽命評估。另外，也針對銲錫接點結構、銲錫接點材料以及UBM組成對電遷移特性的影響做了研究，試著找出影響電遷移可靠度的關鍵因子，並提出優化封裝體的結構及異質材料間之建議方案。

The electromigration reliability of solder interconnects is dominated by current density and temperature inside the interconnects. For flip-chip packages, current densities around the regions where traces connect a solder bump increase by a significant amount owing to the differences in feature sizes and electric resistivities between the solder bump and its adjacent traces. This current crowding effect along with induced Joule heating accelerates electromigration failures. In this paper, effects of current crowding and Joule heating in a flip-chip package are examined and quantified through a three-dimensional electrothermal coupling analysis. We apply a volumetric averaging technique to cope with the current crowding singularity. The volumetrically averaged current density and the maximum temperature in a solder bump are integrated in the Black’s equation to adjust the experimental electromigration fatigue lives. In addition, the effects of the solder bump structure, Sn-37Pb and Sn-Ag-Cu solder bump composition, and UBM composition on the electromigration characteristics are investigated.

1. Tu, K. N., “Recent advances on electromigration in Very-Large-Scale-Integration of interconnects”, Journal of Applied Physics, Vol. 94, No. 9, pp. 5451-5473, 2003.
2. Lau, J. H., Flip Chip Technologies, McGraw-Hill, New York, 1996.
3. Choi, W. J., Yeh, E. C. C. and Tu, K. N., “Mean-time-to-failure study of flip chip solder joints on Cu/Ni(V)/Al thin-film under-bump-metallization”, Journal of Applied Physics, Vol. 94, No. 9, pp. 5665-5671, 2003.
4. Nah, J. W., Paik, K. W., Suh, J. O. and Tu, K. N., “Mechanism of electromigration-induced failure in the 97Pb-3Sn and 37Pb-63Sn composite solder joints”, Journal of Applied Physics, Vol. 94, No. 12, pp. 7560-7566, 2003.
5. Zheng, P. J., Hung, C. Y., Lee, Z. J., Lee, C. W., Chung, C. S. and Wu, J. D., “A comparison of electromigration and thermal fatigue performance between thin and thick film UBM”, Proc. 36th International Symposium on Microelectronics, Boston, MA, pp. 93-99, 2003.
6. Rinne, G. A., “Issues in accelerated electromigration of solder bumps”, Microelectronics Reliability, Vol. 43, No. 12, pp. 1975-1980, 2003.
7. Shao, T. L., Chen, Y. H., Chiu, S. H. and Chen, C., “Electromigration failure mechanisms for SnAg3.5 solder bumps on Ti/Cr-Cu/Cu and Ni(P)/Au metallization pads”, Journal of Applied Physics, Vol. 96, No. 8, pp. 4518-4524, 2004.
8. Lai, Y. S., Lee, C. W., Shao, Y. H. and Liu, Y. H., “Electromigration of Sn-Pb-Ni and Sn-Pb-Cu solder bumps in flip-chip packages”, Proc. 6th International Conference on Electronics Materials and Packaging, Penang, Malaysia, pp. 314-319, 2004.
9. Wu, J. D., Zheng, P. J., Lee, C. W., Hung, S. C. and Lee, J. J., “A study in flip-chip UBM/bump reliability with effects of SnPb solder composition”, Microelectronics Reliability, Vol. 46, No. 1, pp. 41-52, 2006.
10. Lai, Y. S., Lee, C. W., Kao, C. L. and Shao, Y. H., “Influence of test conditions on electromigration reliability of Sn-Ag-Cu flip-chip solder interconnects”, Proc. 38th International Symposium on Microelectronics, Philadelphia, PA, pp. 834-840, 2005.
11. Ye, H., Basaran, C. and Hopkins, D. C., “Thermomigration in Pb-Sn solder joints under joule heating during electric current stressing”, Applied Physics Letters, Vol. 82, pp. 1045-1047, 2003.
12. Basaran, C., Ye, H., Hopkins, D. C., Frear, D. R. and Lin, J. K., “Failure modes of flip chip solder joints under high electric current density”, Journal of Electronic Packaging, Vol. 127, pp. 157-163, 2005.
13. Huang, A. T., Gusak, a. M. and Tu, K.N., “Thermomigration in SnPb composite flip chip solder joints”, Applied Physics Letters, Vol. 88, pp. 141911-141913, 2006.
14. Liang, S. W., Chang, Y. W., Shao, T. L. and Chen, C., “Effect of three-dimensional current and temperature distributions on void formation and propagation in flip-chip solder joints during electromigration”, Applied Physics Letters, Vol. 89, 2006.
15. Lee, T. -Y. T., Lee, T. Y. and Tu, K. N., “A study of electromigration in 3-D flip chip solder joint using numerical simulation of heat flux and current density”, IEEE Transactions on Components and Packaging Technologies, Vol. 27, No. 3, pp. 472-479, 2004.
16. Wang, L., Wu, F., Wu, Y. and Zhang, J., “The effect of current crowding on electromigration in lead-free flip chip bump interconnect”, Proc. 6th IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, Shanghai, China, pp. 224-226, 2004.
17. Black, J. R., “Mass transport of aluminum by momentum exchange with conduction electrons”, IEEE Proceedings of the 6th. Annual Reliability Physics Symposium, pp. 148-159, 1967.
18. Shingubara, S., Miyazaki, S., Sakaue, H. and Takahagi, T., “Evaluation of temperature rise due to joule heating and preliminary investigation of its effect on electromigration reliability”, Stress-Induce Phenomena in Metallization : Sixth Int’l , pp. 94-104, 2002.
19. Black, J. R., “Physics of electromigration”, IEEE Trans. on Electron Devices, pp. 142-149, 1969.
20. Blair, J. C., Ghate, P. G. and Haywood, C. T., “Concerning electromigration in thin films”, Proc IEEE Lett, Vol. 59, pp. 1023-1024, 1971.
21. Yokogawa, S., “Scaling impacts on electromigration in narrow single-damascene Cu interconnects”, Japanese Journal of Applied Physics, Vol. 44, pp. 1717-1721, 2005.
22. Huntington, H. B. and Grone, A. R., “Current-induced marker motion in gold wires”, Journal of Physics and Chemistry of Solids, Vol. 20, No. 1, pp. 76-87, 1961.
23. Shatzkes, M. and Lloyd, J. R., “A model for conductor failure considering diffusion concurrently with electromigration resulting in a current exponent of 2”, Journal of Applied Physics, Vol. 59, No. 11, pp. 3890-3893, 1986.
24. Blech, I. A., “Electromigration in thin aluminium films on titanium nitride”, Journal of Applied Physics, Vol. 47, No. 4, pp. 1203-1208, 1976.
25. De Groot, S. R., “Theorie phenomenologique de L’Effet soret”, Physica, Vol. 9, No. 7, pp. 699-707, 1942.
26. Clement, J. J. and Lloyd, J. R., “Numerical investigations of the electromigration boundary value problem”, Journal of Applied Physics, Vol. 71, No. 4, pp. 1729-1731, 1992.
27. Ye, H., Basaran, C. and Hopkins, D. C., “Numerical simulation of stress evolution during electromigration in IC interconnect lines”, IEEE Transactions On Components And Packaging Technologies, Vol. 26, No. 3, pp. 673-681, 2003.
28. Lai, Y. S. and Kao, C. L., “Electrothermal coupling analysis of current crowding and Joule heating in flip-chip packages”, Microelectronics Reliability, Vol. 46, No. 8, pp. 1357-1368, 2006.
29. JEDEC Solid State Technology Association, JEP154: Guideline for Characterizing Solder Bump Electromigration under Constant Current and Temperature Stress, 2008.
30. Halliday D. and Resnick R., Fundamentals of physics. New York: John Wiley & Sons; 1974.
31. Ellison, G. N., Thermal Computations for Electronic Equipment, R. E. Krieger, Malabar, 1989.
32. Zahn, B. A. and Stout, R. P., “Evaluation of isothermal and isoflux natural convection coefficient correlations for utilization in electronic package level thermal analysis”, Proc. 13th IEEE Semicond. Thermal Measure. Manage. Symp., Austin, TX, pp. 24-31, 1997.
33. Guenin, B. M., Chowdhury, A. R., Groover, R. L. and Derian, E. J., “Analysis of a thermally enhanced ball grid array package”, IEEE Trans. Comp., Pack., Manuf. Technol. – Part A, Vol. 18, No. 4, pp. 749-757, 1995.
34. Manko, H. H., Solder and Soldering, 4th Ed., McGraw-Hill, New York, 2001.
35. Meaden, G. T., Electrical Resistance of Metals, Plenum, New York, 1965.
36. Choi, W. J., Yeh, E. C. C. and Tu, K. N., “Electromigration of flip chip solder bump on Cu/Ni(V)/Al thin film under bump metallization”, Proc. 52nd Electronic Components and Technology Conference, San Diego, CA, pp. 1201-1205, 2002.
37. Darveaux, R., “Effect of simulation methodology on solder joint crack growth correlation and fatigue life prediction”, Journal of Electronic Packaging, ASME, Vol. 124, No. 3, pp. 147-154, 2002.
38. Lai, Y. S., Sathe, S., Kao, C. L. and Lee, C. W., “Integrating electrothermal coupling analysis in the calibration of experimental electromigration reliability of flip-chip packages”, Proc. 55th Electronic Components and Technology Conference, Lake Buena Vista, FL, 2005.
39. Lai, Y. S. and Kao, C. L., “Characteristics of current crowding in flip-chip solder bumps”, Microelectronics Reliability, Vol. 46, No. 5-6, pp. 915-922, 2006.
40. Lai, Y. S., Chen, K. M., Kao, C. L., Lee, C. W. and Chiu, Y. T., “Electromigration of Sn-37Pb and Sn-3Ag-1.5Cu/Sn-3Ag-0.5Cu composite flip-chip solder bumps with Ti/Ni(V)/Cu under bump metallurgy”, Microelectronics Reliability, Vol. 47, No. 8, pp. 1273-1279, 2007.
41. de Orio, R. L., Ceric, H. and Selberherr, S., “Physically based models of electromigration: From Black’s equation to modern TCAD models”, Microelectronics Reliability, Vol. 50, pp. 775-789, 2010.
42. Zhao, X., Wan, Y., Scheuermann, M. and Lim, S. K., “Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs”, In Proceedings of the IEEE International Conference on Computer-Aided Design, San Jose, CA, 2013.
43. Attari, V., Ghosh, S., Duong, T. and Arroyave, R., “On the interfacial phase growth and vacancy evolution during accelerated electromigration in Cu/Sn/Cu microjoints”, Materials Science, arXiv:1803.07227, 2018.