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研究生: 黃宣博
Huang, Hsuan-Po
論文名稱: 低溫下對金氧半場效電晶體的最佳降低供應電壓策略以實現功率效率的最大化
Optimal Strategy of Supply Voltage Scaling with Temperature Lowering for Power Efficiency Maximization of Cryogenic MOSFETs
指導教授: 高國興
Kao, Kuo-Hsing
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2023
畢業學年度: 111
語文別: 英文
論文頁數: 50
中文關鍵詞: 高性能運算量子計算金氧半場效電晶體供應電壓次臨界擺幅
外文關鍵詞: high performance computing and quantum computing, cryogenic MOSFETs, supply voltage, subthreshold swing
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  • 近幾年來,高性能運算 (HPC) 和量子運算 (QC) 受到越來越多的關注。這要歸功於他們更快的分析處理能力。
    高性能運算 (HPC) 可以更有效地處理大規模和複雜的數據。而量子運算 (QC) 能夠解決傳統電腦無法解決的問題。因此,在未來他們將會應用於社會的各個領域,包括工程、生物科技、財經科技、人工智慧、醫療科技等。不過它們對於操作溫度上有嚴格的限制,分別需要在溫度低於300K和4K下。為了更好的發揮實際效益,勢必需要降低整體或元件的功率消耗。
    如何在不犧牲性能 (performance) 的情況下獲得較低的功率消耗,而降低供應電壓的同時降低操作溫度可能會是最佳的解決辦法之一。在這篇碩士論文中,我們首先探討了供應電壓隨溫度變化的關係,並證明了在低溫下,次臨界擺幅的飽和 (SS saturation) 是主要影響的關鍵。本次實驗中使用了tsmc N40 MOSFET並透過 Advance Research System (ARS) probe station進行量測。
    透過量測五種不同供應電壓隨溫度降低變化的策略線,以300K的實驗數據做為參考點,我們比較了不同溫度下元件的操作頻率和功率消耗。同時,我們也觀察到在低溫下的元件特性,包括次臨界擺幅、臨界電壓、載子遷移率以及電導的變化。
    測量結果表明,元件特性在低溫下會達到飽和。為了獲得更好的操作頻率和更低的功率消耗,供應電壓隨溫度的下降有著一定的限制。

    In recent years, high performance computing (HPC) and quantum computing (QC) have received increasing attention. This is attributed to their faster analytical processing power.
    HPC can handle large-scale and complex data more efficiently. And QC can solve problems that cannot be solved by conventional computers. As a result, they will be used in various aspects of society in the future, including engineering, biotechnology, financial technology, artificial intelligence, medical technology and so on. However, they are subject to strict operating temperature limits, requiring temperatures below 300K and 4K respectively. For better practical efficiency, it is necessary to reduce the overall or device power consumption.
    To achieve low power consumption without sacrificing performance, lowering the supply voltage while reducing the operating temperature may be one of the best solutions. In this master thesis, we first investigate the relationship between supply voltage and temperature, and demonstrate that at low temperatures, the subthreshold swing saturation is the main impact factor. In this experiment, tsmc N40 MOSFETs are used and measured with an Advance Research System (ARS) probe station.
    By measuring five strategy lines for different supply voltages as the temperature decreases, using experimental data at 300K as a reference point, we compared the operating frequency and power consumption of the devices at different temperatures. At the same time, we also observed the device characteristics at low temperatures, including variations in subthreshold swing, threshold voltage, carrier mobility and transconductance.
    Measurements demonstrate that the device characteristics saturate at low temperatures. For better operating frequency and lower power consumption, the supply voltage drop with temperature has limitations.

    摘要 I Abstract II 致謝 III Contents IV Table captions VI Figure captions VII Chapter 1 Introduction & Motivation 1-1 Moore`s law and more Moore 1 1-2 Cryogenic-temperature applications (HPC and QC) 9 1-2-1 High performance computing (HPC) 9 1-2-2 Quantum computing (QC) 10 1-3 The need for cryo-CMOS and lower power consumption 13 1-3-1 Importance of Cryo-CMOS 13 1-3-2 Importance of lower power consumption 13 1-4 Benefits of VDD scaling with lowering temperature 15 1-4-1 Methods for reducing total power consumption 15 1-4-2 Feasibility of VDD scaling with lowering temperature 16 1-4-3 Ideal target for VDD scaling with lowering temperature 16 Chapter 2 Device Characteristics at cryogenic temperatures 2-1 Boltzmann statistics and Fermi statistics 18 2-2 Threshold voltage, carrier mobility and subthreshold swing 20 2-2-1 Threshold voltage variation at cryogenic temperature 20 2-2-2 Carrier mobility variation at cryogenic temperature 21 2-2-3 Subthreshold swing variation at cryogenic temperature 21 Chapter 3 Experimental Details 3-1 Methodology for VDD (T) formulation 26 3-2 Definition of performance extraction 27 3-3 VDD (T) scaling strategy considering SS saturation 29 3-4 Device under test and experiment 30 Chapter 4 Results and Discussion 4-1 N40 devices Characteristics Measured at VDD (T) 39 4-1-1 Current-Voltage of N40 devices measured at VDD (T) 39 4-1-2 Current over drain bias-Voltage of N40 devices measured at VDD (T) 39 4-1-3 Subthreshold swing of N40 devices measured at VDD (T) 40 4-1-4 Mobility and threshold voltage of N40 devices measured at VDD (T) 41 4-2 Transconductance variation of N40 devices measured at different VDD (T) 42 4-3 Electrical performance comparison of N40 devices measured at different VDD (T) 44 4-4 Frequency and power consumption comparison of N40 devices measured at different VDD (T) 45 Chapter 5 Conclusion and Future work 5-1 Conclusion 47 5-2 Future work 47 References 48

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