積體電路在現代生活中的應用隨處可見，尤其是在消費性電子產品中已成為不可或缺的一部分，極大地提高了人類的生產效率和生活便捷性。其中內部的電子元件扮演著至關重要的角色。提升晶片封裝產品 中良品數的比率、更高的傳輸效率、更小的體積以及更優越的散熱性能，是目前技術發展的重要目標。在晶片封裝生產週期的前段，須通過模擬和驗證的方式預測產品的性能以及各種可能發生的缺陷。本研究著重於生產週期前段的製程改良，目的是為了最佳化封裝產品的幾何尺寸。
為了達到此目的，作者與工業與資訊管理學系的研究生黃鈺淇一同開發了人工智慧自動化校正系統，該系統將有限元素商用軟體 Ansys與人工智慧（ AI）模型結合透過 AI模型找出材料的最佳參考溫度組合，使有限元素模型預測的翹曲量與實驗值相匹配。在驗證完成有限元素封裝模型及其參考溫度組合後，再次利用人工智慧自動化校正系統來最佳化封裝的幾何尺寸。最終目的是使封裝產品達到較小的翹曲量，提高產品的可靠性和性能。

Integrated circuits are essential in modern life, particularly in consumer electronics, where they significantly enhance productivity and convenience. The electronic components within these devices are crucial to their functionality. Current technological advancements focus on increasing chip packaging yield rates, achieving higher transmission efficiency, reducing size, and improving thermal performance. Early-stage simulation and verification in the chip packaging production cycle are critical for predicting product performance and identifying potential defects. The present study aims to optimize the geometric dimensions of packaging products through early-stage process improvements.
This study developed an artificial intelligence (AI) automated correction system that integrates commercial finite element software, Ansys, with AI models. The AI model identifies the optimal reference temperature combination of materials to ensure the warpage predicted by the finite element model matches experimental values. After validating the finite element packaging model and its reference temperature combinations, the AI automated correction system is employed to further optimize the geometric dimensions of the packaging. The goal is to minimize warpage in packaging products, thereby enhancing their reliability and performance.

[1]B. Zhou et al., "Smart home energy management systems: Concept, configurations, and scheduling strategies," Renewable and Sustainable Energy Reviews, vol. 61, pp. 30-40, 2016.
[2]Z. Zhang and C. Wong, "Recent advances in flip-chip underfill: materials, process, and reliability," IEEE transactions on advanced packaging, vol. 27, no. 3, pp. 515-524, 2004.
[3]K.-N. Tu and K. Zeng, "Tin–lead (SnPb) solder reaction in flip chip technology," Materials science and engineering: R: reports, vol. 34, no. 1, pp. 1-58, 2001.
[4]W.-C. Chuang and W.-L. Chen, "Study on the Strip Warpage Issues Encountered in the Flip-Chip Process," Materials, vol. 15, no. 1, p. 323, 2022.
[5]Y. Sawada, K. Harada, and H. Fujioka, "Study of package warp behavior for high-performance flip-chip BGA," Microelectronics Reliability, vol. 43, no. 3, pp. 465-471, 2003.
[6]S. Yamada, "A mechanism for board warpage by thermal expansion of surface mounted connector," IEEE transactions on components, hybrids, and manufacturing technology, vol. 9, no. 4, pp. 508-512, 1986.
[7]R. Beica, "Flip chip market and technology trends," in 2013 Eurpoean Microelectronics Packaging Conference (EMPC), 2013: IEEE, pp. 1-4.
[8]J. H. Lau, "Recent advances and new trends in flip chip technology," Journal of Electronic Packaging, vol. 138, no. 3, p. 030802, 2016.
[9]K. DeHaven and J. Dietz, "Controlled collapse chip connection (C4)-an enabling technology," in 1994 Proceedings. 44th Electronic Components and Technology Conference, 1994: IEEE, pp. 1-6.
[10]E. Suhir, "An approximate analysis of stresses in multilayered elastic thin films," 1988.
[11]G. G. Stoney, "The tension of metallic films deposited by electrolysis," Proceedings of the Royal Society of London. Series A, Containing Papers of a Mathematical and Physical Character, vol. 82, no. 553, pp. 172-175, 1909.
[12]S. Timoshenko, "Analysis of bi-metal thermostats," Josa, vol. 11, no. 3, pp. 233-255, 1925.
[13]M.-Y. Tsai, C. J. Hsu, and C. O. Wang, "Investigation of thermomechanical behaviors of flip chip BGA packages during manufacturing process and thermal cycling," IEEE Transactions on Components and Packaging Technologies, vol. 27, no. 3, pp. 568-576, 2004.
[14]J.-H. Zhao, X. Dai, and P. S. Ho, "Analysis and modeling verification for thermal-mechanical deformation in flip-chip packages," in 1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No. 98CH36206), 1998: IEEE, pp. 336-344.
[15]M.-Y. Tsai, Y.-C. Chen, and S. R. Lee, "Correlation between measurement and simulation of thermal warpage in PBGA with consideration of molding compound residual strain," IEEE Transactions on Components and Packaging Technologies, vol. 31, no. 3, pp. 683-690, 2008.
[16]M.-Y. Tsai, H.-Y. Chang, and M. Pecht, "Warpage analysis of flip-chip PBGA packages subject to thermal loading," IEEE Transactions on Device and Materials Reliability, vol. 9, no. 3, pp. 419-424, 2009.
[17]D.-L. Chen et al., "Reliability Prediction and Improvement of Board-Level Thermal Cycling Test for Molded Flip-Chip Ball-Grid-Array Package," in 2023 IEEE 25th Electronics Packaging Technology Conference (EPTC), 2023: IEEE, pp. 995-998.
[18]I. Goodfellow, Y. Bengio, and A. Courville, Deep learning. MIT press, 2016.
[19]D. E. Rumelhart, G. E. Hinton, and R. J. Williams, "Learning representations by back-propagating errors," nature, vol. 323, no. 6088, pp. 533-536, 1986.
[20]G. E. Hinton, S. Osindero, and Y.-W. Teh, "A fast learning algorithm for deep belief nets," Neural computation, vol. 18, no. 7, pp. 1527-1554, 2006.
[21]R. Tibshirani, "Regression shrinkage and selection via the lasso," Journal of the Royal Statistical Society Series B: Statistical Methodology, vol. 58, no. 1, pp. 267-288, 1996.
[22]S. Wang, B. Ji, J. Zhao, W. Liu, and T. Xu, "Predicting ship fuel consumption based on LASSO regression," Transportation Research Part D: Transport and Environment, vol. 65, pp. 817-824, 2018.
[23]M.-C. Kang, D.-Y. Yoo, and R. Gupta, "Machine learning-based prediction for compressive and flexural strengths of steel fiber-reinforced concrete," Construction and Building Materials, vol. 266, p. 121117, 2021.
[24]S. K. Panigrahy, Y.-C. Tseng, B.-R. Lai, and K.-N. Chiang, "An overview of AI-Assisted design-on-Simulation technology for reliability life prediction of advanced packaging," Materials, vol. 14, no. 18, p. 5342, 2021.
[25]W.-C. Chuang and W.-L. Chen, "Investigation of Strip Warpage Behavior in Wire Bonding Process," Journal of Electronic Packaging, vol. 142, no. 2, p. 021002, 2020.
[26]M. Stecher, "The moiré phenomenon," American Journal of Physics, vol. 32, no. 4, pp. 247-257, 1964.
[27]D. Roylance, "Stress-strain curves," Massachusetts Institute of Technology study, Cambridge, 2001.
[28]S. Park, H. Lee, B. Sammakia, and K. Raghunathan, "Predictive model for optimized design parameters in flip-chip packages and assemblies," IEEE Transactions on Components and Packaging Technologies, vol. 30, no. 2, pp. 294-301, 2007.
[29]M.-Y. Tsai, C. Ting, C. Huang, and Y.-S. Lai, "Determination of residual strains of the EMC in PBGA during manufacturing and IR solder reflow processes," Microelectronics Reliability, vol. 51, no. 3, pp. 642-648, 2011.
[30]N. R. E. Lim, R. Dimagiba, A. Ubando, J. Gonzaga, and G. Augusto, "FEA of thermal warpage in ball grid array with consideration of molding compound residual strain compared to experimental measurements," in 2018 IEEE 10th International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM), 2018: IEEE, pp. 1-5.