摘 要
　　本論文主要針對UWB 射頻收發機CMOS晶片進行研究與製作。論文中首先研製CMOS寬頻低雜訊放大器，而後整合寬頻低雜放大器、寬頻driver 放大器、及T/R switch於單一UWB收發機射頻前端電路CMOS射頻晶片中。晶片製作均使用TSMC CMOS 0.18μm製程，晶片量測皆採用打鎊線至PCB測試板上進行。
　　吾人利用回授原理，設計三顆non-cascode寬頻低雜訊放大器。在3-6 GHz CMOS UWB低雜訊放大器方面，量得增益為14~15.8dB，輸入及輸出返回損耗分別大於12dB及10dB，隔離度大於21dB、雜訊指數4.5~6dB、IIP3約為-5dBm、input P1dB為-15dBm，在電源為1.8V下電流消秏33mA，即功率消耗為59.4mW。1V/6mA低功率3-6 GHz CMOS UWB低雜訊放大器是改良前一顆晶片而設計，晶片量測結果就UWB low band(3.1GHz~5.15GHz)而言，當Vdd=1.8V/1.0V時，消耗功率為25.2mW/6mW，其增益為16.2~17.4dB/11.7~13.7dB，雜訊指數為3.8dB~4.3dB/4.3~4.9dB，輸入返回損耗大於9.8dB/13.2dB，輸出返回損耗大於11dB/10.6dB，input P1dB大於-19dBm/-21dBm，IIP3大於-9.2dBm/-10.8dBm。2.4-6GHz CMOS UWB差動式低雜訊放大器，量測結果在UWB low band 頻段，其增益為17.6 ~ 18.3dB，雜訊指數為3.4dB~5.2dB，輸入返回損耗大於10dB，輸出返回損耗大於11dB，input P1dB為-17dBm，IIP3為-7.3dBm。
　　3-6 GHz CMOS UWB收發機射頻前端電路， 發射電路量測結果在UWB low band頻段，當Vdd=1.8V/1.0V時，其增益為16.3~18dB/14.3~16.4dB，雜訊指數為3.5dB~4.6dB/3.7~4.8dB，輸入返回損耗大於9.3dB/9.7dB，輸出返回損耗大於10.3dB/10.5dB，output P1dB為-2.2dBm/-4.2dBm，OIP3為6.3dBm/5.6dBm。接收電路量測結果在UWB low band頻段，當Vdd=1.8V/1.0V時，其增益為13.5~16.6dB /10.6~14dB，雜訊指數為5.1dB~6.4dB/5.2~6.6dB，輸入返回損耗大於10dB/10.9dB，輸出返回損耗大於9.6dB/10dB，input P1dB為-21dBm/-21dBm，IIP3為-10.1dBm/-10.9dBm。
另外，吾人設計一5-11 GHz CMOS UWB低雜訊放大器及一3-11 GHz SiGe UWB低雜訊放大器，其模擬與量測結果置於附錄中。

Abstract

　This thesis presents the research on RF transceiver CMOS chips for UWB (Ultra Wide-Band). Research CMOS broadband LNA at first in the thesis, and then combine broadband LNA, broadband driver amplifier, and T/R switch in single chip of UWB CMOS RF transceiver. The RFICs are fabricated by a TSMC standard 0.18μm CMOS process. The circuit measurement is performed using a FR-4 PCB test fixture.
　I utilize the principle of feedback, to design three non-cascode broadband LNA. About the 3-6GHz CMOS UWB LAN, the measured gain is 14~15.8dB, noise figure is 4.5~6dB, input return loss is better than 12dB, output return loss is better than 10dB, and input P1dB is -15dBm, IIP3 is -5dBm, isolation better than 21dB. About the 1V 6mA 3-6GHz CMOS UWB LAN, in the UWB low band (3.1 to 5.15GHz) under 1.8V/1.0V supply voltage, the broadband LNA exhibit a gain of 16.2~17.4dB/ 11.7~13.7dB, noise figure is 3.8dB~4.3dB/4.3~4.9dB, input return loss better than 9.8dB/13.2dB, output return loss better than 11dB/10.6dB, isolation better than 34dB/35dB, IIP3 of -9.2dBm/-10.8dBm and input P1dB of -19dBm/-21dBm, respectively. About the 2.4-6GHz COMS UWB differential LNA, in the UWB low-band, the broadband LNA exhibit a gain of 17.6~18.3dB, noise figure of 3.4dB~5.2dB, input return loss better than 10 dB, output return loss better than 11 dB, isolation better than 30dB, IIP3 of -7.3dBm and input P1dB of -17 dBm, respectively.
　About the 3-6GHz CMOS RF front-end of UWB transceiver, in the UWB low band under 1.8V/1.0V supply voltage, the transmit circuits (driver amp. + T/R switch) exhibit a gain of 16.3~18dB/14.3~16.4dB, noise figure is 3.5dB~4.6dB/3.7~4.8dB, input return loss better than 9.3dB/9.7dB, output return loss better than 10.3dB/ 10.5dB, OIP3 of 6.3dBm/5.6dBm and output P1dB of -2.2dBm/-4.2dBm, respectively. the receive circuits (T/R switch + LNA) exhibit a gain of 13.5~16.6dB/10.6~14dB, noise figure is 5.1dB~6.4dB/5.2~6.6dB, input return loss better than 10dB/10.9dB, output return loss better than 9.6dB/10dB, IIP3 of -10.1dBm/-10.9dBm and input P1dB of -21dBm/-21dBm, respectively.
Besides, I design a 5-11GHz CMOS UWB LNA and a 3-11GHz SiGe UWB LNA. The measured results are in the appendix A and appendix B.

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