二維材料在新世代電子元件中具有極大潛力，但降低接觸電阻與抑制高介電常數材料所引入的介面陷阱，仍是提升二維 TMD 元件效能的關鍵挑戰，因此接觸與介面工程變得至關重要。
本研究針對 WSe₂ 為通道材料的場效電晶體（FET），探討介面與接觸工程策略。為改善閘極控制與降低介面陷阱，我們在 WSe₂ 與高介電常數 HfO₂ 介電層之間插入數奈米厚的 hBN 緩衝層。電性量測結果顯示，hBN 插入可大幅降低次臨界擺幅（SS）與介面陷阱密度（Dit），顯示其具有效的陷阱鈍化能力並提升電場調控效果。
在接觸工程方面，透過比較 10 nm 與 20 nm 的 Cr 緩衝層，我們發現兩者 SS 表現幾乎相同，代表 10 nm Cr 已足以緩衝高能金屬粒子對 WSe₂ 的衝擊。我們也比較了分段（stepwise）與連續金屬沉積的差異，結果顯示熱累積對元件表現影響有限。進一步降低鍍金速率（由 0.38 nm/min 降至 0.13 nm/min）則能有效減少表面損傷，SS 由約 3571 mV/dec 降至 296 mV/dec，電性顯著提升。
整體而言，本研究結果提供了接觸製程的具體優化方向，並為高-κ介電層中二維材料元件的製作與效能提升奠定基礎。

Two-dimensional materials hold great promise for next-generation electronics; however, reducing contact resistance and mitigating interface traps introduced by high-κ dielectrics remain critical challenges, making contact and interface engineering essential for achieving high-performance 2D FETs.
This study investigates interface and contact engineering strategies to enhance the performance of WSe₂‑based field‑effect transistors (FETs). To improve gate control and suppress interface traps, a few‑nanometer‑thick hexagonal boron nitride (hBN) layer was inserted between the WSe₂ channel and a high‑κ HfO₂ gate dielectric. Electrical measurements demonstrate that hBN insertion yields a pronounced improvement in subthreshold swing (SS) and reduces interface trap density (Dᵢₜ) by over an order of magnitude, confirming effective trap passivation and stronger electrostatic control.
In the contact engineering study, we evaluated the role of a Cr buffer layer by comparing devices with 10 nm versus 20 nm Cr beneath a PdAu contact. Both configurations showed nearly identical SS, this suggests that a 10 nm Cr layer is sufficiently thick to serve as an effective buffer, alleviating the strong interaction between high-energy atoms and the WSe₂ surface. To probe potential thermal effects, we compared segmented (stepwise) deposition against continuous deposition and observed negligible differences in device metrics, suggesting thermal accumulation is minimal under our conditions. Crucially, reducing the metal deposition rate from 0.38 nm/min to 0.13 nm/min suppressed deposition‑induced damage, leading to a reduction in SS from approximately 3571 mV/dec to about 296 mV/dec.
These findings provide valuable insights into the contact deposition processes used in our laboratory and help us understand methods which can be used to achieve better switching in our devices, as well as providing a starting point to understand how performance in devices with high-κ dielectrics can be enhanced as well as the challenges faced in fabricating these devices.

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