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研究生: 尤磊安
Rehman, Khalil ur
論文名稱: 以電腦輔助設計模擬金氧半電晶體和穿隧式電晶體閘極氧化物微縮效應
Gate Oxide scaling Effect on MOSFETs and TFETs by TCAD Simulations
指導教授: 高國興
Kao, Kuo-Hsing
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 奈米積體電路工程碩士博士學位學程
MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年: 2018
畢業學年度: 106
語文別: 英文
論文頁數: 33
外文關鍵詞: Tunnel Field-effect-transistor, Metal-oxide-semiconductor field effect transistor, Band-to-band tunneling, Gate-oxide scaling, Equivalent-Oxide-Thickness
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  • The need of continue scaling, mobile and IoT applications has increased the demand for the devices of low supply voltage and low-leakage operations. Tunnel field effect transistors (TFETs) have potential to overcome the fundamental sub-threshold limitation of 60 m V/dec limit of the traditional metal-oxide-semiconductor field effect transistor (MOSFET). The TFET has been proposed as replacement for the MOSFET while the fundamental power issue faced by the traditional MOSFET as device scaling continues the demand of Moore’s law. The TFET is the promising option as an emerging transistor for further scaling down the supply voltage, threshold voltage and power consumption of integrated circuits (ICs).
    In this thesis the effect of gate oxide scaling on the MOSFET and TFET is investigated. We have simulated MOSFETs and TFETs with different equivalent-oxide-thickness (EOT), using Sentaurus TCAD. The comparison of obtained results shows that EOT scaling influences the electrical characteristics of a TFET more significantly, and a thinner EOT improves the devices performance in terms of a higher on-current and steeper subthreshold slope. EOT scaling has less effect on the MOSFET devices performance. The simulation results were also compared to experimental results, and they were in a good agreement.

    Contents Abstract I Acknowledgments II List of Tables VI List of Figures VII Chapter 1 Introduction and Motivation 1 1.1 Power Dissipation Issues in MOSFET 1 1.2 Traditional MOSFET, Subthreshold Swing (SS) and Sub-60 Devices 2 1.3 Challenges of TFET Technologies 5 1.4 Motivation and Organization of the Thesis 6 Chapter 2 Introduction to TFET Device Physics and Simulation Methodology 8 2.1 Tunnel Field Effect Transistor (TFET) 8 2.2 Basic Structure and Working Principle of TFET 8 2.3 TFET Characteristics 10 2.3.1 Transfer Characteristics of TFET 10 2.3.2 Output Characteristics of TFET 12 2.4 Introduction to Synopsys Sentaurus TCAD 13 2.5 Physical Models used in TCAD Simulation 14 2.5.1 Band-to-Band Tunneling 14 2.5.2 Fermi Statistics 15 2.5.3 Shockely-Read-Hall and Trap-Assisted Tunneling 16 2.6 Physics Section in SentaurusDevice 17 Chapter 3 Gate Oxide scaling effect on MOSFET and TFET 18 3.1 Equivalent-Oxide-Thickness 18 3.2 Gate oxide scaling methods and their effect on MOSFET and TFET 19 3.3 Device structure and simulation settings using Sentaurus TCAD 21 3.4 Results Analysis and Discussion 22 3.4.1 EOT scaling effect on MOSFET and TFET. 22 3.4.2 Impact of gate scaling on band diagram 23 3.5 Analytical Model 24 3.6 Comparison of Analytical Model and TCAD Simulations 26 Chapter 4 Conclusion and Future Direction 27 4.1 Conclusion 27 4.2 Future Directions 28 4.2.1 Adding traps in TCAD simulation study 28 4.2.2 Single crystal device fabrication 28 4.2.3 Gate oxide scaling effect on NC-FET 28 References 29 References in chapter 1 29 References in chapter 2 29 References in Chapter 3 30 References in Chapter 4 33

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