隨著半導體封裝技術朝向高密度、薄型化發展，面板級封裝因具有高生產效率、低成本與良好線路整合能力，逐漸成為先進封裝技術中的重要發展方向。而面板級封裝的結構是由多種異質材料所組成，各材料間熱膨脹係數與機械性質不同，當封裝體進行熱循環測試時，容易在材料介面與幾何不連續處產生熱應力集中，進而導致裂縫、脫層與可靠度失效等問題。
本論文針對面板級封裝結構依照AEC-Q101的車用規格條件，使用有限元素分析軟體ANSYS-Workbench，探討元件於熱循環測試條件下的熱應力分佈情形。研究結果顯示，原始封裝結構的最大等效應力為200.44 MPa，應力集中發生於晶片導通孔及異質材料交界處。而本文選定雷射鑽孔開口尺寸、ABF厚度、晶片厚度及RDL厚度作為控制因子，找出最佳化結構設計組合後，將其重新代入有限元素模型進行驗證，最大等效應力降低至72.60 MPa，下降約63.78%。且後續實際投料並經熱循環可靠度測試與電子顯微鏡檢測後，未觀察到明顯脫層現象。由此可知，本論文所建立之有限元素分析結合田口方法，能有效改善面板級封裝結構之熱應力分佈，降低介面脫層風險，並提升產品可靠度與設計開發效率。

This study focuses on the structural optimization of embedded panel-level package electronic components under thermal cycling test conditions. The objective is to reduce thermal stress concentration at material interfaces and via regions, thereby lowering the risk of delamination and improving package reliability. A finite element model was established using ANSYS-Workbench to simulate the thermal stress distribution of the original package structure according to the automotive reliability requirements of AEC-Q101. The maximum equivalent stress in the die region was selected as the evaluation index. To optimize the package structure, the Taguchi L9 orthogonal array was applied with four control factors: laser via opening size, ABF thickness, die thickness, and RDL thickness.The simulation results showed that the maximum equivalent stress of the original structure was 200.44 MPa, mainly concentrated around the die via and heterogeneous material interfaces. Based on the S/N ratio analysis, the optimal parameter combination was determined as A3B1C1D3. After re-simulation, the maximum equivalent stress was reduced to 72.60 MPa, corresponding to a stress reduction of approximately 63.78%. In addition, the optimized structure was fabricated and verified through thermal cycling reliability testing and C-SAM inspection, and no obvious delamination was observed. These results indicate that finite element analysis combined with the Taguchi method can effectively improve thermal stress distribution and enhance the reliability of embedded panel-level packages.

1. 張協智，"利用田口方法進行疊合封裝體可靠度之最佳化設計"，國立成功大學工程科學系碩士論文，2012。
2. Lau, J. H., "Thermal Stress Analysis of Plastic Leaded Chip Carriers," Proceedings of the InterSociety Conference on Thermal Phenomena in Electronic Systems (ITHERM), 1990.
3. 陳東陽，"電子構裝的熱應力分析"，國立成功大學土木工程系專題研究計畫成果報告，2000。
4. 郭昱綸，"覆晶球柵陣列電子封裝體在溫度循環下的熱應力與熱應變分析”，國立中山大學機械與機電工程研究所碩士論文，2003。
5. NASA Jet Propulsion Laboratory, "Analysis of Plastic Parts Package Delamination", JPL D-31227, 2005.
6. 李育嘉，"對堆疊式晶片構裝疲勞壽命之最佳化探討"，國立成功大學工程科學系碩士論文，2005.
7. 許豐庭，2006，”高頻覆晶封裝之熱應力分析”， 國立交通大學機械工程學系碩士論文。
8. Li, H. Y., Chua, H. M., Che, F. X., Trigg, A. D., Teo, K. H., and Gao, S., "Redistribution Layer Process Development and Improvement for 3D Interposer", In Proceedings of the 2011 13th Electronics Packaging Technology Conference (EPTC), 2011.
9. Lei, W., and Kumar, A., "Delamination and Reliability Issues in Packaged Devices", Chapter 7 in Adhesion in Microelectronics, 1st Edition, pp. 267-312, 2014.
10. 王保雄，"扇出型玻璃基板封裝設計之失效壽命預估及驗證研究"，國立清華大學動力機械工程學系博士論文，2020.
11. Wu, X., Wang, Z., Ma, S., Chu, X., Li, C., Wang, W., Jin, Y., and Wu, D., "An RDL Modeling and Thermo-Mechanical Simulation Method of 2.5D/3D Advanced Package Considering the Layout Impact Based on Machine Learning", Micromachines, Vol. 14, No. 8, Article No. 1531, 2023.
12. Mao, K.H., Kuo, C., Tan, V., Chou, A., "Panel Level Package (PLP)–Scaling up Fan-Out Packaging", As originally published in SMTA proceedings, pp. 60-67, 2024.
13. Chery, E., Duval, F. F.C., Stucchi, M., Slabbekoorn, J., Croes, K., and Beyne, E., "Reliability Study of Polymers Used in Sub-4-μm Pitch RDL Applications", IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 11, No. 7, pp. 1073-1080, 2021.
14. Yu, Y., Ha, J., Park, M., Yang, E., and Kim, M., " Delamination between Dielectric Layers of FOPLP due to Copper Residue under High Temperature Storage Conditions", Proceedings of the 2022 IEEE 24th Electronics Packaging Technology Conference (EPTC), pp. 766-770, 2022.
15. Zhou, S., Zhong, C., Shan, L., Li, J., He, C., and Huang, D., "Stress Analysis of Typical Structure of Redistribution Layer of Fan-Out Wafer Level Package", Proceedings of the 2022 23rd International Conference on Electronic Packaging Technology (ICEPT), 2022.
16. 陳建羽，"以田口實驗方式進行IC封裝元件翹曲之數值模擬"，逢甲大學機械工程研究所碩士班碩士論文，2006。
17. 許登凱，"電子封裝體受熱循環應力之疲勞壽命分析與可靠度研究"，國立台灣大學機械工程學系碩士論文，2007。
18. 李輝煌，"田口方法-品質設計的原理與實務"，高立圖書，2004。
19. ANSYS, Inc., "Applications for Electronics in ANSYS Mechanical 2019 R2", Workshop Manual, 2019.