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研究生： 陳佳偉
Chen, Jia-Wei
論文名稱： 混合式電晶體在低溫下之特性探討
Behavior of Hybrid FET characteristic at cryogenic temperature
指導教授： 江孟學
Chiang, Meng-Hsueh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年： 2023
畢業學年度： 111
語文別： 英文
論文頁數： 38
中文關鍵詞： 鰭式電晶體 、低溫 、橫向擴散金氧半場效電晶體(LDMOS)
外文關鍵詞： FinFET, cryogenic temperature, LDMOS
相關次數： 點閱：102  下載：28 
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    • 在這個科技日新月異的時代，為了追求元件高速、低功耗的特性，低溫電子學越來越受到關注。許多研究表明，在低溫下操作MOSFET有許多優點，包括更好的次臨界擺伏、更高的載子遷移率以及較低的導通電阻等。然而，對於常作為I/O元件的橫向擴散金氧半場效電晶體(LDMOS)而言，其在低溫下的特性是否更加優異，是值得我們探討的。
    在本篇論文中，我們量測了混合式電晶體的電性，其結構結合了鰭式通道與平面飄移區以實現更好的導通電阻。藉由量測其在低溫下的特性，我們探討了LDMOS在低溫下的表現以及其背後的物理機制，以作為未來應用在低溫下的LDMOS設計的參考。

    In this rapidly evolving era of technology, there is increasing interest in cryogenic electronics to achieve high-speed and low-power characteristics in electronic components. Many studies have shown the advantages of operating MOSFETs at low temperatures, including improved subthreshold swing, higher carrier mobility, and lower on-resistance. However, for laterally diffused metal-oxide-semiconductor (LDMOS) devices commonly used as I/O components, it is important to investigate whether their characteristics are further enhanced at low temperatures.
    In this thesis, we measured the electrical properties of hybrid transistors that combine fin-channel and planar drift regions to achieve improved on-resistance. By measuring their performance at low temperatures and exploring the underlying physical mechanisms, we investigated the behavior of LDMOS devices as a reference for future designs of LDMOS for cryogenic temperature applications.

    摘要 I Abstract II Contents III Table Captions V Figure Captions VI Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 2 1.3 Overview of the Thesis 3 Chapter 2 Review of LDMOS and Physics in Cryogenic Temperature 4 2.1 LDMOS Structure 4 2.2 Breakdown Mechanism 5 2.2.1 Punch-through Breakdown 5 2.2.2 Dielectric Breakdown 6 2.2.3 Avalanche Breakdown 6 2.3 Specific On-resistance 7 2.4 Key Cryogenic Temperature Phenomenon in CMOS 8 2.4.1 Subthreshold Swing in Cryogenic Temperature 8 2.4.2 Incomplete Ionization and Carrier Freeze-out 9 2.4.3 Mobility 12 Chapter 3 Hybrid FET 15 3.1 Hybrid FET Structure 15 3.2 Device Design 17 3.3 The Method of Parametric Extraction 20 3.3.1 Threshold Voltage 20 3.3.2 Subthreshold Swing 20 3.3.3 Ion/Ioff Ratio 20 3.3.4 Drain Induced Barrier Lowering 21 3.3.5 Ron and Breakdown Voltage 21 Chapter 4 Device Characteristics in Cryogenic Temperatures 22 4.1 FinFET Characteristics in Cryogenic Temperatures 22 4.2 Hybrid FET Characteristics in Cryogenic Temperatures 26 Chapter 5 Conclusion 35 Chapter 6 Future Work 36 Reference 37

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