光學效率(OE)在CMOS感光元件中是相當重要之指標，目前已知深溝槽隔離(DTI)結構與倒金字塔陣列(IPA)結構是能有效地提高光學效率之方法。近年來，因應車用感測器與人臉辨識系統等智慧晶片之需求，開始著重於研發近紅外光(NIR)波段之影像感測器。CMOS感光元件之製程十分複雜，往往要到接近後端之製程，才能藉由量測，測出感光性能，若能先預先了解DTI結構與IPA結構對於OE之影響，可以減少製程上之時間與成本。
CMOS感光元件主要透過矽感光二極體(Photodiode)進行光子吸收。本研究透過Lumerical/FDTD光學模擬軟體，藉由有限差分時域法(FDTD)建立三維(3-D)背照式(Back-side)CMOS感光元件模型，分析NIR波段下，波長從700nm到1000nm之OE值。從模擬結果得知，在近紅外光波段下，當DTI深度增加，OE值隨著提高，然而當DTI深度到達5000nm時，OE值之提升幅度會趨緩。因光線在像素內產生全內反射(Total internal reflection)行為，使得光程(Optical path length)在像素內增長。從模擬結果得知，IPA結構相對於平面結構，會提升OE值。因IPA結構根據蝕刻角度呈現54.7°，藉由表面角度之不同，光線進入像素時，產生光捕捉(Light trapping)現象。根據分析不同IPA尺寸，得知在IPA結構尺寸為500nm時，OE值最高。

Optical efficiency(OE) is a very important indicator in CMOS image sensor. Deep trench isolation(DTI) structures and inverted pyramid array(IPA) structurea are knowm to be effective ways to improve optical efficiency. In recent years, in response to the demand for smart chip such as automotive sensors and face recongnition systems, we have developed on the image sensors in the near-infrared(NIR) band. The process of CMOS sensor is very complicated, and it is often close to the finished product to measure the photosensitivity. If we can understand the influence of DTI structure and IPA structure on the OE value, we can reduce the time on the process and the cost.
The CMOS sensor mainly performs photon absorption through a photodiode. In this study, through the Lumerical/FDTD optical simulation software, a three-domensional(3-D) back-side CMOS sensor model was established by finite difference time domain method(FDTD) to analyze the wavelength from 700nm to 1000nm in the NIR band. As the DTI depth increases, the OE value increases. However, when the DTI depth reaches 5000nm, the increase in the OE value has been slow down. Because the light produces a total internal reflection behavior within the pixel, so the optical path length grows within the pixel. From the simulation results, the IPA structure increases the OE value relative to the planar structure. According to the analysis of different IPA sizes, it is found that the OE value is the highest when the IPA structure size is 500 nm. Since the IPA structure exhibits 54.7 degrees according to the etching angle, due to the difference in surface angle, light trapping occurs when light enters the pixel.
Keywords : FDTD；CMOS；DTI；IPA；OE。

INTRODUCTION
In recent years, with the rapid development of CMOS photosensitive elements, their use has become more and more extensive. From mobile phone lens and vehicle image sensors to high-sensitivity machine vision chips, today, not only high resolution but also high resolution is required. Better imaging at low light sources, ie with a higher QE. In the low light source, in addition to capturing less visible light, there is also near-infrared light that can not be seen by the naked eye to capture light, to achieve better imaging results, and to achieve good imaging results in both day and night vision environments. In measuring the QE value, it is often necessary to process the entire CMOS photosensitive wafer to the finished product stage to have the effect of measurement. In this study, numerical simulation can be used to simulate the influence of the structure on the OE value, saving cost and time throughout the process. In order to improve the QE value, in addition to the internal circuit design to improve the photon conversion electron efficiency, it can also start from the perspective of increasing the absorption efficiency of light absorption. In the low light source, it is necessary to improve the sensitivity, and the light absorption is especially improved for CMOS photosensitive elements. important.
METHOD
The OE value of the light absorption efficiency is increased by structural changes, thereby indirectly increasing the QE value. At present, the most important OE value is the back-illuminated and DTI structure. According to the current research literature, the surface which is originally a flat surface can be etched into an IPA structure by wet etching, and the angle change caused by the crystal orientation is used to increase the light absorption in the structure. Based on the above reasons, this study hopes to establish a set of three-dimensional CMOS models with back-illuminated DTI and IPA structures. First explore the relationship between DTI and OE values, and then add the effect of IPA structure on OE values.
RESULTS
1.Lumerical/FDTD numerical simulation: This study uses Lumerical optical analysis software, the same value of the same structure and the incident light wavelength range, the simulation results and the actual output CMOS photosensitive film measurement results, the error value is about 5%
2.3D CMOS sensor model: Establish a 3D CMOS sensor model in FDTD. Compared with the 2D CMOS sensor model, the 3D CMOS sensor model can not only describe the Bayer array in a complete way, but also set the light wave closer to the true measurement source.
3.DTI structure: The DTI structure is placed in a CMOS sensor model. The light produces a total internal reflection behavior within the pixel, causing the optical path to grow within the pixel, thereby increasing the OE value. At different DTI depths, the OE value is increased, and the OE value is also increased. When the DTI depth reaches 5000 nm, the increase in the OE value is slowed down. Therefore, in terms of process, the DTI depth can be designed to be 5000 nm, which is more in line with the cost of the process.
4.IPA structure: The IPA structure is placed in a CMOS sensor. At the same DTI depth, the OE value of the CMOE photosensitive element having the IPA structure is high. Since the wet etching angle is 54.7°, light capturing occurs when light enters the pixel due to the difference in surface angle. The IPA size is related to the pixel size, and the pixel size affects the number of IPA structures. In design, the IPA size is 500 nm, and the light absorption efficiency is the best

[1] X. Liu, CMOS image sensors dynamic range and SNR enhancement via statistical signal processing, in, stanford university, 2002.
[2] A.E. Gamal, H. Eltoukhy, CMOS image sensors, IEEE Circuits and Devices Magazine, 21 (2005) 6-20.
[3] L.J. Kozlowski, J. Luo, W. Kleinhans, T. Liu, Comparison of passive and active pixel schemes for CMOS visible imagers, in: Infrared Readout Electronics IV, International Society for Optics and Photonics, 1998, pp. 101-111.
[4] B. Pain, T. Cunningham, S. Nikzad, M. Hoenk, T. Jones, C. Wrigley, B. Hancock, A back-illuminated megapixel CMOS image sensor, (2005).
[5] A. Tournier, F. Leverd, L. Favennec, C. Perrot, L. Pinzelli, M. Gatefait, N. Cherault, D. Jeanjean, J. Carrere, F. Hirigoyen, Pixel-to-pixel isolation by deep trench technology: Application to CMOS image sensor, in: IISW, 2011.
[6] L. Meng, J. Yan, Effect of process parameters on sidewall damage in deep silicon etch, Journal of Micromechanics and Microengineering, 25 (2015) 035024.
[7] Y. Kitamura, H. Aikawa, K. Kakehi, T. Yousyou, K. Eda, T. Minami, S. Uya, Y. Takegawa, H. Yamashita, Y. Kohyama, Suppression of crosstalk by using backside deep trench isolation for 1.12 μm backside illuminated CMOS image sensor, in: 2012 International Electron Devices Meeting, IEEE, 2012, pp. 24.22. 21-24.22. 24.
[8] R. Ramanath, W.E. Snyder, G.L. Bilbro, W.A. Sander, Demosaicking methods for Bayer color arrays, Journal of Electronic imaging, 11 (2002) 306-316.
[9] A. Sultana, E. Kamrani, M. Sawan, CMOS silicon avalanche photodiodes for NIR light detection: a survey, Analog Integrated Circuits and Signal Processing, 70 (2012) 1-13.
[10] J. Vaillant, A. Crocherie, F. Hirigoyen, A. Cadien, J. Pond, Uniform illumination and rigorous electromagnetic simulations applied to CMOS image sensors, Opt. Express, 15 (2007) 5494-5503.
[11] A. Crocherie, J. Vaillant, F. Hirigoyen, Three-dimensional broadband FDTD optical simulations of CMOS image sensor, SPIE, 2008.
[12] F. Hirigoyen, A. Crocherie, J. Vaillant, Y. Cazaux, FDTD-based optical simulations methodology for CMOS image sensor pixels architecture and process optimization, 2008.
[13] J.-K. Lee, A. Kim, D.-W. Kang, B.Y. Lee, Efficiency enhancement in a backside illuminated 1.12 μm pixel CMOS image sensor via parabolic color filters, Opt. Express, 24 (2016) 16027-16036.
[14] R. Abdolvand, F. Ayazi, An advanced reactive ion etching process for very high aspect-ratio sub-micron wide trenches in silicon, Sensors and Actuators A: Physical, 144 (2008) 109-116.
[15] A. Mavrokefalos, S. Eon Han, S. Yerci, M. Branham, G. Chen, Efficient Light Trapping in Inverted Nanopyramid Thin Crystalline Silicon Membranes for Solar Cell Applications, 2012.
[16] S. Yokogawa, I. Oshiyama, H. Ikeda, Y. Ebiko, T. Hirano, S. Saito, T. Oinoue, Y. Hagimoto, H. Iwamoto, IR sensitivity enhancement of CMOS Image Sensor with diffractive light trapping pixels, Scientific Reports, 7 (2017) 3832.
[17] I. Oshiyama, S. Yokogawa, H. Ikeda, Y. Ebiko, T. Hirano, S. Saito, T. Oinoue, Y. Hagimoto, H. Iwamoto, Near-infrared sensitivity enhancement of a back-illuminated complementary metal oxide semiconductor image sensor with a pyramid surface for diffraction structure, in: 2017 IEEE International Electron Devices Meeting (IEDM), IEEE, 2017, pp. 16.14. 11-16.14. 14.
[18] Y. Kane, Numerical solution of initial boundary value problems involving maxwell's equations in isotropic media, IEEE Transactions on Antennas and Propagation, 14 (1966) 302-307.
[19] A. Taflove, S.C. Hagness, Computational electrodynamics: the finite-difference time-domain method, Artech house, 2005.
[20] R. Courant, K. Friedrichs, H. Lewy, On the Partial Difference Equations of Mathematical Physics, IBM Journal of Research and Development, 11 (1967) 215-234.
[21] J.-P. Berenger, A perfectly matched layer for the absorption of electromagnetic waves, Journal of Computational Physics, 114 (1994) 185-200.
[22] B. Jean-Pierre, Perfectly Matched Layer (PML) for Computational Electromagnetics, Morgan & Claypool, 2007.
[23] B.E. Bayer, Color imaging array, in, Google Patents, 1976.
[24] J. Robertson, R.M. Wallace, High-K materials and metal gates for CMOS applications, Materials Science and Engineering: R: Reports, 88 (2015) 1-41.
[25] H. Tsugawa, H. Takahashi, R. Nakamura, T. Umebayashi, T. Ogita, H. Okano, K. Iwase, H. Kawashima, T. Yamasaki, D. Yoneyama, Pixel/DRAM/logic 3-layer stacked CMOS image sensor technology, in: 2017 IEEE International Electron Devices Meeting (IEDM), IEEE, 2017, pp. 3.2. 1-3.2. 4.
[26] K.E. Bean, Anisotropic etching of silicon, IEEE Transactions on Electron Devices, 25 (1978) 1185-1193.
[27] T. Chao, Introduction to semiconductor manufacturing technology.
[28] A. Michelmore, J.D. Whittle, J.W. Bradley, R.D. Short, Where physics meets chemistry: Thin film deposition from reactive plasmas, Frontiers of Chemical Science and Engineering, 10 (2016) 441-458.
[29] C. Craigie, T. Sheehan, V. Johnson, S. Burkett, A.J. Moll, W. Knowlton, Polymer thickness effects on Bosch etch profiles, Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, 20 (2002) 2229-2232.
[30] C. Chang, Y.-F. Wang, Y. Kanamori, J.-J. Shih, Y. Kawai, C.-K. Lee, K.-C. Wu, M. Esashi, Etching submicrometer trenches by using the Bosch process and its application to the fabrication of antireflection structures, Journal of micromechanics and microengineering, 15 (2005) 580.
[31] C. Kuo-Shen, A.A. Ayon, Z. Xin, S.M. Spearing, Effect of process parameters on the surface morphology and mechanical performance of silicon structures after deep reactive ion etching (DRIE), Journal of Microelectromechanical Systems, 11 (2002) 264-275.
[32] H. Seidel, L. Csepregi, A. Heuberger, H. Baumgärtel, Anisotropic etching of crystalline silicon in alkaline solutions I. Orientation dependence and behavior of passivation layers, Journal of the electrochemical society, 137 (1990) 3612-3626.
[33] U. Abidin, B.Y. Majlis, J. Yunas, Fabrication of pyramidal cavity structure with micron-sized tip using anisotropic KOH etching of silicon (100), Jurnal Teknologi, 74 (2015).
[34] S.C. Baker‐Finch, K.R. McIntosh, Reflection of normally incident light from silicon solar cells with pyramidal texture, Progress in Photovoltaics: Research and Applications, 19 (2011) 406-416.
[35] G. Yun, K. Crabtree, R.A. Chipman, Three-dimensional polarization ray-tracing calculus I: definition and diattenuation, Appl. Opt., 50 (2011) 2855-2865.
[36] M. Dresselhaus, Solid state physics part ii optical properties of solids, (2001).
[37] Y. Kim, W. Choi, D. Park, H. Jeoung, B. Kim, Y. Oh, S. Oh, B. Park, E. Kim, Y. Lee, T. Jung, Y. Kim, S. Yoon, S. Hong, J. Lee, S. Jung, C. Moon, Y. Park, D. Lee, D. Chang, A 1/2.8-inch 24Mpixel CMOS image sensor with 0.9μm unit pixels separated by full-depth deep-trench isolation, in: 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 84-86.
[38] I. Zagorodnov, R. Schuhmann, T. Weiland, A uniformly stable conformal FDTD‐method in Cartesian grids, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 16 (2003) 127-141.
[39] W. Yu, R. Mittra, A conformal FDTD software package modeling antennas and microstrip circuit components, IEEE Antennas and Propagation Magazine, 42 (2000) 28-39.
[40] D.C. BV, D. HYDRAULICS, Absorption spectroscopy, (1962).
[41] R. Azzam, C.L. Spinu, Achromatic angle-insensitive infrared quarter-wave retarder based on total internal reflection at the Si–SiO 2 interface, JOSA A, 21 (2004) 2019-2022.
[42] Y. Kitamura, H. Aikawa, K. Kakehi, T. Yousyou, K. Eda, T. Minami, S. Uya, Y. Takegawa, H. Yamashita, Y. Kohyama, T. Asami, Suppression of crosstalk by using backside deep trench isolation for 1.12μm backside illuminated CMOS image sensor, in: 2012 International Electron Devices Meeting, 2012, pp. 24.22.21-24.22.24.
[43] F. Hirigoyen, 1.1 μm Backside Imager vs. Frontside Imager: an optics-dedicated FDTD approach, in: 2009 International Image Sensor Workshop, Norway, 2009.