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研究生: 陳品崴
Chen, Pin-Wei
論文名稱: 基於共享緩衝區與展開管線化技巧且可支援多種回授模式之超高吞吐量安全加密系統
Ultra High-Throughput Cryptosystem for Feedback Operation Modes Based on Shared Buffer and Unrolled-Pipeline Techniques
指導教授: 卿文龍
Chin, Wen-Long
學位類別: 碩士
Master
系所名稱: 工學院 - 工程科學系
Department of Engineering Science
論文出版年: 2023
畢業學年度: 111
語文別: 中文
論文頁數: 73
中文關鍵詞: 區塊加密回授工作模式共享緩衝區高吞吐量VLSI架構設計
外文關鍵詞: block cipher, mode of operation, shared buffer, high throughput, VLSI architecture
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  • 摘要 i 致謝 xvi 目錄 xvii 圖目錄 xx 表目錄 xxii 第一章 導論 1 1.1 前言 1 1.2 文獻探討 2 1.3 研究動機 7 1.4 論文架構 8 第二章 區塊加密與工作模式 9 2.1 區塊加密簡介 9 2.2 工作模式介紹 10 2.2.1 多種工作模式 10 2.2.2 具有回授的工作模式 10 2.2.2.1 密碼塊連結(CBC) 10 2.2.2.2 密文回饋(CFB) 11 2.2.2.3 輸出回饋 (OFB) 12 2.2.3 無回授的工作模式 13 2.2.3.1 電子密碼本(ECB) 13 2.2.3.2 計數器模式(CTR) 14 2.2.4 模式比較 15 2.3 支援回授模式的重要性與目前已知瓶頸 17 第三章 架構分析與問題探討 19 3.1 分析傳統區塊加密架構 19 3.1.1 單回合架構 19 3.1.2 單回合架構搭配管線化技巧 20 3.1.3 管線化展開架構 21 3.2 實現加速之應用場景 22 3.3 分析加速區塊加密之基本架構 24 3.3.1 子通道之定義 24 3.3.2 專屬記憶體搭配平行管線化展開架構 24 3.3.3 專屬記憶體搭配平行單回合架構 25 3.3.4 專屬記憶體搭配單一管線化展開架構 26 3.4 分析本篇提出基於共享緩衝區之高速加密架構 27 3.5 各架構之統整與比較 28 3.6 設計挑戰與規劃之設計方法 29 3.6.1 共享緩衝區的演算法設計之困難 29 3.6.2 共享緩衝區的演算法驗證過程複雜 29 3.6.3 本研究規劃之設計方法與流程 29 第四章 提出電路架構之實現方法 32 4.1 本篇共享緩衝區之運作流程與架構設計 32 4.2 基於動態鏈結串列方法與三種佇列結構實現共享緩衝區 34 4.2.1 浮動佇列 (FQ) 35 4.2.2 輸出佇列 (OQ) 35 4.2.3 可用佇列 (AQ) 36 4.2.4 三種佇列的運作機制與關係 36 4.2.5 本篇使用共享緩衝區的重要規則 37 4.3 整體電路架構設計 38 4.3.1 接收端電路 (Rx) 39 4.3.1.1 資料管理模組 41 4.3.1.2 佇列管理模組 41 4.3.2 傳送端電路 (Tx) 43 4.3.2.1 佇列管理模組 45 4.4 參數化設計共享緩衝區 47 4.5 加密電路之電路設計 48 4.5.1 AES加密運算 48 4.5.1.1 加密步驟 48 4.5.1.2 位元組取代 (SubBytes) 49 4.5.1.3 列移位 (ShiftRows) 51 4.5.1.4 混合行 (MixColumns) 51 4.5.1.5 回合金鑰加法 (AddRoundKey) 53 4.5.2 本篇使用之加密電路架構 53 第五章 效能分析與實驗數據 56 5.1 以加速比評量加速效果 56 5.2 軟體評估結果與硬體執行結果相符 57 5.3 共享緩衝區大小與加速比提升之關聯 58 5.4 共享緩衝區與專屬記憶體加速效果之比較 59 5.5 本篇架構在不同通道數與管線化級數之情況下的加速效果 61 5.1 電路合成結果與比較 63 5.2 以FPGA進行設計雛形(prototyping)驗證 65 5.2.1 開發環境 65 5.2.2 驗證流程與結果 66 第六章 結論與未來展望 68 參考文獻 69

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