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研究生: 羅盛郅
Lou, San-ji
論文名稱: 應用於超寬頻接收機之寬頻CMOS平衡器及分散式切換開關 RFIC與3-5-GHz射頻接收模組之研製
Design of Broadband CMOS Balun, Distributed T/R Switch RFICs and 3-5-GHz RF Receiver Module For UWB Receiver Applications
指導教授: 莊惠如
Chuang, Huey-Ru
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2006
畢業學年度: 94
語文別: 中文
論文頁數: 106
中文關鍵詞: 寬頻平衡器分散式切換開關射頻接收模組
外文關鍵詞: Broadband balun, Distributed T/R switch, RF receiver module
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  • 本論文主要針對UWB 射頻收發機CMOS晶片以及3-5-GHz射頻接收模組進行研究與製作,CMOS晶片包括3-5-GHz寬頻平衡器電路及DC-20-GHz T/R 切換開關,晶片製作均使用國家晶片中心(CIC)提供的TSMC 0.18 μm製程。寬頻平衡器電路與T/R切換開關均採用on-wafer量測。
    3-5-GHz寬頻被動平衡器之量測結果顯示,在頻帶內S21 > -7 dB,S31 > -6 dB。振幅差異小於2.7 dB,相位差異介在172˚至189˚之間,與理想值180˚之相位偏差(phase imbalance)小於9˚,輸入返回損耗大於13 dB。
    DC-20-GHz 分散式T/R切換開關其量測結果顯示,各Port之返回損耗S11 <-10 dB、S22 <-10 dB、S33 <-12 dB;導通時之S21 >-6.3 dB、S31 >-6 dB;不導通時之S21 <-17 dB、S31 <-17 dB;T/R之間隔離度S23 <-19.9 dB。Input P1 dB大於13 dBm,IIP大於19 dBm。
    3-5-GHz射頻接收模組使用離散元件製作,包括3-5-GHz超寬頻低雜訊放大器,3-5-GHz帶通濾波器,3-5-GHz混波器(乘法器),3.9-4.1-GHz 0°/90°移相器,3-5-GHz等化器,3-5-GHz功率分配器,DC-1-GHz低通濾波器,DC-1-GHz低頻放大器。量測結果顯示,整合以上電路所製作之I-arm接收機模組其整體增益大於17.1 dB,最大增益變化量約為3.4 dB,OIP3約為8.9 dBm,input P1 dB約為-19.7 dBm。考量IQ解調功能後之I-arm接收機模組整體增益大於14.4 dB,最大增益變化量約3.2 dB,IIP3為1.9 dBm,系統之Input P1 dB約為-19 dBm。整合後3-5-GHz射頻接收模組具有6 dB上之整體增益,IQ不平衡小於2 dB。最大增益變化量為4.5 dB。

    Passive CMOS RFICs based on TSMC 0.18μm CMOS technology which is offered by National Chip Implementation Center (CIC ) and 3-5GHz RF receiver module for UWB radio frequency receiver are mainly researched and fabricated. The RF integrated chips including broadband passive balun and 20GHz T/Rswitch are presented. Both circuits were measured by on-wafer test .
    In 3 to 5GHz band, the broadband balun exhibit a amplitude imbalance less than 2.7dB, a phase imbalance less than 9˚ between 172˚ to 189˚, the input return loss higher than 13 dB, S21 > -7dB , S31 > -6dB.
    From DC to 20 GHz , the distributed T/R switch exhibit the return loss higher then 10dB at input port and two ouput port , S21 > -3dB and S31 > -3.3dB below 20GHz when operating in on-state, both S21 and S31 less then -45dB below 20GHz when operating in off-state. The isolation is higher then 34dB ,the 1-dB compression points is 13 dBm at 20GHz , and the IIP3 is 25dBm at 20GHz.
    In 3 to 5GHz band, the RF receiver module was made by lumped elements , which includes 3-5-GHz UWB LNA , 3-5-GHz BPF , 3-5-GHz mixer , 3.9-4.1-GHz 0°/90° phase shifter , 3-5-GHz equalizer , 3-5-GHz power divider , DC-1-GHz LPF , DC-1-GHz amplifier . The measurement result shows that the I-arm cuircuit of the receiver module exhibit a convertion gain higher then 17.1 dB , gain difference of 3.4 dB , the OIP3 is 8.9 dBm and the P1dB is -19.7 dBm . The I-arm circuit which include IQ demodulation function exhibit a convertion gain higher then 14.4 dB , gain difference of 3.2 dB , the OIP3 is 1.9 dBm and the P1dB is -19 dBm .The 3-5-GHz RF module exhibit a total gain higher then 6 dB, the IQ imbalance lesser then 2 dB , the highest gain difference is 4.5 dB.

    第一章 緒論 Introduction 1 1.1 UWB的研究背景 1 1.2 UWB的定義 2 1.3 UWB的特性 3 1.4 UWB的系統架構 5 1.5 DS-CDMA與MB-OFDM 技術比較 7 1.6 無線個人網路及無線區域網路通訊協定 9 1.7 論文架構 12 第二章 UWB收發機之寬頻3-5-GHz CMOS被動式平衡器 13 2.1 平衡器電路簡介 13 2.2 寬頻3-5-GHz CMOS被動式平衡器電路設計 14 2.2.1 電路架構 14 2.2.2 電路原理 14 2.2.3 2nd order lattice balun 18 2.2.4 模擬與量測結果 21 2.2.5 結果與討論 23 第三章 DC-20-GHz CMOS分散式射頻開關 25 3.1 T/R切換開關簡介 25 3.1.1 PIN Diode 切換開關 26 3.1.2 GaAs MESFET 切換開關 27 3.1.3 CMOS 切換開關 27 3.2 Body-Floating架構 29 3.2.1 利用Body-floating架構降低插入損失[14] 29 3.2.2 利用body-floating架構提升線性度[13] 31 3.3 DC-20-GHz分散式CMOS T/R切換開關電路設計 35 3.3.1 電路設計 35 3.3.2 模擬與量測結果 40 3.3.3 結果與討論 43 第四章 3-5-GHz DS-UWB射頻接收模組 45 4.1 鏈路預算(Link budget) 45 4.2 DS-UWB射頻接收模組設計簡介 46 4.3 3-5-GHz Hybrid Low Noise Amplifier 47 4.3.1 設計流程與模擬結果 47 4.3.2 實作與量測結果 49 4.4 3-5-GHz Monolithic Amplifier 52 4.4.1 3-5-GHz Monolithic Amplifier (#1)實作與量測結果 52 4.4.2 3-5-GHz Monolithic Amplifier (#2)實作與量測結果 55 4.5 3-5-GHz BroadBand Mixer 57 4.5.1 實作與量測結果 57 4.6 3-5-GHz BroadBand Microstrip Bandpass Filter (BPF) 58 4.6.1設計流程與模擬結果 58 4.6.2 BPF(#1)實作與量測結果 59 4.6.3 BPF(#2)實作與量測結果 60 4.7 DC-1-GHz Lowpass Filter (LPF) 60 4.7.1 設計流程與模擬結果 60 4.7.2 實作與量測結果 61 4.8 DC-1-GHz Baseband Amplifier 62 4.8.1 實作與量測結果 62 4.9 3-5-GHz Equalizer(含衰減器) 65 4.9.1 設計流程與模擬結果 65 4.9.2 實作與量測結果 66 4.10 4-GHz Microstrip Quadrature Hybrid 67 4.10.1 設計流程與模擬結果 67 4.10.2 實作與量測結果 68 4.11 3-5-GHz Wilkinson Divider 70 4.11.1 設計流程與模擬結果 70 4.11.2 實作與量測結果 71 4.12 以個別子電路串聯量測I-Arm電路接收效能 73 4.13 整合部份個別子電路串聯量測I-Arm電路接收效能 74 4.14 考量IQ解調電路之I-Arm電路接收效能量測 77 4.15 3-5-GHz DS-UWB 射頻接收機模組設計過程討論 80 4.16 3-5-GHz DS-UWB射頻接收模組製作與量測 86 4.17 結果與討論 88 第五章 結論 89 參考文獻 90 附錄A 分散式主動電路的概論 93 A.1 分散式電路系統 93 A.1.1 無限長傳輸線 93 A.1.2 有限長傳輸線 95 A.1.3 射頻積體電路中的有限長傳輸線種類 98 附錄B UWB 3-5-GHz接收模組使用元件規格表 103 B. 1 BPF620_E7764規格表 103 B. 2 Mini Circuits Amp ERA-2SM 規格表 105 B. 3 Mini Circuits Frequency Mixer規格表 106

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