成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	羅大惟 Lo, Ta-Wei
論文名稱：	釘架氧化程度對引腳型封裝結構脫層之研究 Delamination study of lead frame oxidation on lead-typed semiconductor packages
指導教授：	趙隆山 Chao, Long-Sun
學位類別：	碩士 Master
系所名稱：	工學院 - 工程科學系碩士在職專班 Department of Engineering Science (on the job class)
論文出版年：	2015
畢業學年度：	103
語文別：	中文
論文頁數：	81
中文關鍵詞：	半導體封裝、脫層、釘架氧化、釘架設計型式
外文關鍵詞：	Assembly, De-lamination, Lead frame oxidization, Lead frame design
相關次數：	點閱：110 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

此論文主要在研究引腳型半導體封裝產品在製程過程中，釘架氧化對半導體封裝後脫層的影響，主要考慮在半導體封裝製程中一定會經高溫的製程，釘架在經過高溫烘烤後會產生氧化的現象，研究中利用控制烤箱的烘烤環境及最佳化烤箱腔體內部的含氧量，改善釘架的氧化程度，進而改善釘架與膠餅之間的脫層缺點，並進行銲線在釘架上的品質檢測。由於釘架氧化會影響釘架與膠餅間的結合力，所以在此次的研究中也探討了釘架型式的設計，包括在釘架背面加上凹洞以及各種晶片座環路型式，以強化釘架與膠餅之間的結合力。歸納出烤箱參數為抽風口徑15mm、電子風扇轉速1000rpm、氮氣流量85LPM的最佳烘烤環境以及最佳的釘架設計，並將兩者納入標準的封裝製程規範中，以提高產品的品質可靠性。

This article is to study the effect of the leadframe oxidation on the delamination inside lead-typed semiconductor packages during packaging assembly processes. As some of the assembly step is operating with high temperature, the leadframe would have oxidation reaction on the surface during the process, which could possibly induce package delamination afterward. Therefore, in our Design of Experiment, we define control factors of curing oven environment, oxygen content and also study different design of leadframe shape, including the die paddle size and shape, adding dimple on the surface. These factors are defined to control the level of oxidation on the leadframe surface, in order to prevent the delamination between the leadframe and molding compound. In addition, the wire bonding performance data would be collected and examed to make sure no side effects.
In summary, after the DOE, the optimize process recipe for oven are the exhausting pipe diameter of 15 mm, the electric fan speed of 1000 rpm, and the nitrogen flow rate of 85 LPM. Together with the optimized leadframe design to be implemented to assembly process, the quality level of delamination control is improved.

中文摘要……………………………………...…………………………………....Ⅰ
英文摘要……………………………………...…………………………………....Ⅱ
誌謝………………...………………….………………………………................ⅤII
目錄……………………………...……..…………………………………...........ⅥII
表目錄…………………………………..………………………………………....XI
圖目錄…………………………………………………………...……………….ⅩII
符號……………………………..……………………………………………….ⅩVI
第一章 緒論……….………………………………………………………………..1
1-1 前言….……………………………………………………………………...1
1-2 研究動機與目的…………………………………….……………………...2
1-3 文獻回顧…………………………………………….……………………...7
第二章 半導體封裝製程及可靠度測試介紹………….........….………………10
2-1半導體封裝製程介紹...................................................................................10
2-1-1晶圓背面研磨............................................................................................11
2-1-2晶圓安置....................................................................................................12
2-1-3晶圓切割....................................................................................................14
2-1-4晶粒黏合....................................................................................................15
2-1-5銀膠烘烤....................................................................................................17
2-1-6電漿清洗....................................................................................................17
2-1-7銲線............................................................................................................18
2-1-8封膠............................................................................................................19
2-1-9穩定烘烤....................................................................................................19
2-1-10印字..........................................................................................................20
2-1-11去膠去緯..................................................................................................20
2-1-12電鍍..........................................................................................................21
2-1-13去框/成型.............................................................................................22
2-1-14外觀檢驗..................................................................................................23
2-1-15包裝..……………………………………………………………………23
2-2半導體封裝產品可靠度測試介紹...............................................................24
2-2-1半導體封裝產品可靠度測試項目............................................................25
2-2-1-1短期可靠度測試…………………….....................................................26
2-2-1-2長期可靠度測試.....................................................................................27
2-2-2半導體封裝產品可靠度之驗證機制........................................................30
第三章 半導體封裝之脫層介紹………………...........…………………………..35
3-1材料基本特性介紹.......................................................................................35
3-1-1釘架製程....................................................................................................35
3-1-2銀膠特性....................................................................................................45
3-2釘架與環氧樹脂（EMC）間脫層介紹............................................................50
3-3半導體封裝製程改善及檢測方法...............................................................51
3-4材料外觀改善及檢測方法...........................................................................53
第四章 實驗結果與討論……………………………………………….......…......54
4-1半導體封裝製程實驗結果與討論...............................................................54
4-1-1半導體封裝製程實驗設計及步驟............................................................54
4-1-2半導體封裝製程實驗結果........................................................................60
4-1-2-1各實驗組別之烤箱腔體內部含氧量.....................................................60
4-1-2-2烤箱腔體內部含氧量製程參數效應分析….........................................60
4-1-2-3烤箱腔體內部含氧量最佳化參數確認實驗結果.................................62
4-1-2-4各實驗組別之脫層缺點比率.................................................................63
4-1-2-5各實驗組別之脫層缺點比率最佳化結果.............................................64
4-1-2-6脫層缺點比率對應烤箱最佳化參數確認實驗結果.............................66
4-1-2-7最佳化實驗組別的表面分析.................................................................67
4-2材料外觀實驗結果討論...............................................................................70
4-2-1釘架上增加凹洞設計應力模擬結果........................................................70
4-2-2布丁膜實驗結果........................................................................................70
4-2-3各式晶片座設計........................................................................................71
4-2-4各式晶片座設計應力模擬結果................................................................73
4-2-5實際產品驗證結果....................................................................................75
第五章 結論與未來研究方向…………………………........................…....…….77
5-1 結論………………………………………………………........…………..77
5-2 未來研究方向……………………………………………….....………….78
參考文獻………………………………………….………………….....………….79
附錄………………………………………………………………..……………….81

                                    

[1] Denni Yu, “Reliability introduction”, ASEKH QA Lab, Feb 2005.
[2] Jessamine Chung, “SAT introduction”, ASEKH QA Lab, Jul 2003.
[3] Chai Tai Clhong , Alan Leslie, Lim 'Thiam ELeng, “Investigation on the Effect of Copper Leaclframe Oxidation on Package Delamination”, IEEE, 1995.
[4] Taylor and Francis, “Effect of the microstructure of copper oxide on the adhesion behavior of epoxy/copper leadframe joints”, 02 Apr 2012.
[5] Soon-Jin Cho, Kyung-Wook Paik and Young-Gil Kim “The Effect of Oxidation of Cu-base Leadframe on the Interface Adhesion Between Cu Metal and Epoxy Mounding Compound”, May 1997.
[6] W.D. Driel, H.K.L. Bressers, H.J. Janssen, A. Bielen, X. Yan, P.M.P. Stevens, G.Q. Zhang, "A Study on the Effect of Mold Compound Moisture Related Properties and Leadframe Dimension on the Reliability of IC Packages Using An Integrated Mechanical Modeling Approach," IEEE Transactions on Components and Packaging Technologies, vol. 31, pt. 2, pp. 260-268, 2008.
[7] A.A.O. Tay, T.Y. Lin, “Influence of Temperature, Humidity and Defect Location on Delamination in Plastics Packages,” IEEE Trans. Compon Pack Manuf Technol, vol. 22, pp.512–8, 1999.
[8] R. Schmidt, W. Hosler, R. , Tilgner, “RBS Measurement of the Thickness of Nanometer Oxide Layers: Adhesion Strength Between Copper Leadframe and Molding Compound Correlated With the Oxide Layer Thickness,” ,1997
[9] T.S. Tong, J.K.“A Study and Investigation on Processes Inducing Delamination in QFN Package Using Statistical Analysis,” International Electronic Manufacturing Technology, pp.381-389, 2006.
[10] H. Lee, “Electro De-flash Instruction,” ASEKH PE, 2008.
[11] Chung Chang “Assembly flow Presentation”, ASEKH Process Engineer Department, Jun 2006.
[12] “OKAMOTO GRINDING WHEEL”, OKAMOTO. Electronics, Apr 2004
[13] Brian Huang “Wafer Mount Training”, ASEKH Process Engineer Department, Feb 2001
[14] “Blade Concept introduction”, 家榮股份有限公司, May 2006.
[15] “Plasma Clean introduction”, ASEKH RD Lab, Aug 2002.
[16] “RELIABILITY CONDITION”, JEDEC, May 2005.
[17] Jessamine Chung “SAT Introduction and Application”, ASEKH QA Lab, Jul 2007.
[18] “Lead Frame 製程簡介”, ASEMTL, May 2002.
[19] “Presentation of SET Company Profile”, SUMIKO Electronics Taiwan, Nov
2004.
[20] “General Introduction to Die Attach Materials”, Ablestik Nation Starch and
Chemical Company, Mar 2005.
[21] “Epoxy 組成成份與基本特性簡介”, ASEKH Technology Department, Mar
2003.
[22] “Pudding mold instruction”, Kyocera Chemical Corporation, Dec 2004.
[23] “FTIR原理”, PerkinElmer Taiwan, Jul 2004.

校內：2025-08-01公開
校外：2025-08-01公開

簡易檢索 / 詳目顯示

相關論文